21 A/D CONVERTER (ADC10)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
21-5
RS: Source impedance
RAIN: Analog input resistance
CAIN: Analog input capacitance
AVDD
VSS
RAIN
RS
AINx
CAIN
3.5.1 Equivalent Circuit of Analog Input Portion
Figure 21.
Determine fADCLK and ADST[2:0] settings to satisfy the expression below.
tACQ = 8
× (RS + RAIN) × CAIN
(See “Electrical Characteristics” for the RAIN and CAIN values.)
1
————
× (Number of clock cycles set by ADST[2:0]) > tACQ
fADCLK
fADCLK: A/D conversion clock frequency [Hz]
Setting Conversion Result Storing Mode
21.3.6
The A/D converter loads the 10-bit conversion results into ADD[15:0]/ADC10_ADD register (16-bit register) after
an A/D conversion has completed. At this time, the 10-bit conversion results are aligned in the 16-bit register ac-
cording to the conversion result storing mode set with STMD/ADC10_TRG register either as the high-order 10 bits
(left justify mode) or the low-order 10 bits (right justify mode). The remaining six bits are all set to 0.
ADD bit
15
...
10
9
...
6
5
...
0
Left justify mode (STMD = 1) (MSB)
10-bit conversion results
(LSB)
0
...
0
Right justify mode (STMD = 0)
0
...
0
(MSB)
10-bit conversion results
(LSB)
3.6.1 Conversion Data Alignment
Figure 21.
A/D Conversion Control and Operations
21.4
The A/D converter should be controlled in the sequence shown below.
1. Activate the A/D converter.
2. Start A/D conversion.
3. Read the A/D conversion results.
4. Terminate A/D conversion.
Activating A/D Converter
21.4.1
After the settings described in Section 21.3 have been completed, write 1 to ADEN/ADC10_CTL register to enable
the A/D converter. The A/D converter is thereby ready to accept a trigger to start A/D conversion. To set up the A/D
converter again, or when the A/D converter is not used, ADEN must be set to 0.
Starting A/D conversion
21.4.2
The A/D converter starts A/D conversion when a trigger is input while ADEN is 1. When software trigger is select-
ed, an A/D conversion starts by writing 1 to ADCTL/ADC10_CTL register.
The A/D converter accepts triggers from only the trigger source selected by ADTS[1:0]/ADC10_TRG register.
Once a trigger is input, the A/D converter starts sampling of the analog input signal and A/D conversion beginning
with the conversion start channel selected by ADCS[2:0]/ADC10_TRG register.
The software trigger bit ADCTL functions as an A/D conversion status bit that goes 1 while A/D conversion is un-
derway even if it has started by another trigger source. The channel in which conversion is underway can be identi-
fied by reading ADICH[2:0]/ADC10_CTL register.