19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
19-35
ISIF is set to 1 when the operation that is specified and triggered using the USI_ISTGx register has
completed. At the same time an operation completion interrupt request is sent to the ITC if ISIE/USI_
ISIEx register is 1. ISIF is reset by writing 1.
Precautions
19.9
Interface mode setting
Be sure to perform software reset (USIMOD[2:0]/USI_GCFGx register = 0x0) and set the interface mode (USI-
MOD[2:0]/USI_GCFGx register = 0x1, 0x2, 0x4, or 0x5) before changing other USI configurations.
Busy flags
The busy flags listed below may be set with delay. When checking the busy status after performing an operation
that sets the busy flag, wait for at least one T16F output clock cycle before reading the flag. If the busy flag is
read with no wait time inserted, the flag may not indicate the current status properly.
9.1 Busy Flags and Delay Conditions
Table 19.
Interface mode
Busy flag
Timing with delay occurred
UART mode
UTBSY/USI_UIFx register After transmit data is written to the transmit data buffer
SPI master mode SSIF/USI_SIFx register
After transmit data is written to the transmit data buffer in normal
mode (No delay will occur in fast mode.)
I2C master mode IMBSY/USI_IMIFx register After the trigger bit is set
I2C slave mode
ISBSY/USI_ISIFx register After the trigger bit is set
PCLK
T16F output clock
Transmit data buffer
Transmit shift register
Busy flag
Wait time
DA
The busy flag can be checked.
9.1 Waiting Before Reading Busy Flag
Figure 19.
Receiving control byte in I2C slave mode
The external I2C master device sends a control byte to the I2C slave device when an ACK has been received af-
ter sending a slave address. The subsequent operations of the slave device are determined by the control byte.
SDA line
1: Write (by master)
0: Read (by master)
11: Reserved
10: 32-bit address
01: 16-bit address
00: 8-bit address
Start condition
D7
D6
D5
D4
D3
D2
D1
D0
STA
Reserved
Addr size R/W
ACK
R/W
ACK
Slave address
Access address
Control byte
9.2 Control Byte Sent from I
Figure 19.
2C Master
I2C master write (data receiving from master)
SDA line
Start condition
Write
16-bit address
and data write
STA
Stop condition
Access address
STP
ACK
Slv_Addr
Addr[15:8]
ACK
Addr[7:0]
ACK
DA0
ACK
DA1
0x02
Write data
0
9.3 I
Figure 19.
2C Master Write (Data Receiving from Master)
The control byte specifies the access address size and writing operations. The received data that follow the
control byte should be used as the address and the data to be written according to the access address size.