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3 MEMORY MAP, BUS CONTROL
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
3-5
Internal Peripheral Area
3.4
The I/O and control registers for the internal peripheral modules are located in the 1K-byte area beginning with ad-
dress 0x4000 and the 4K-byte area beginning with address 0x5000.
For details of each control register, see the I/O register list in Appendix or description for each peripheral module.
Internal Peripheral Area 1 (0x4000–)
3.4.1
The internal peripheral area 1 beginning with address 0x4000 contains the I/O memory for the peripheral functions
listed below.
MISC register (MISC, 8-bit device)
UART (UART, 8-bit device)
Fine mode 16-bit timers (T16F, 16-bit device)
16-bit timers (T16, 16-bit device)
Interrupt controller (ITC, 16-bit device)
SPI (SPI, 16-bit device)
I2C master (I2CM, 16-bit device)
I2C slave (I2CS, 16-bit device)
Internal Peripheral Area 2 (0x5000–)
3.4.2
The internal peripheral area 2 beginning with address 0x5000 contains the I/O memory for the peripheral functions
listed below.
Clock timer (CT, 8-bit device)
Stopwatch timer (SWT, 8-bit device)
Watchdog timer (WDT, 8-bit device)
Clock generator (CLG, 8-bit device)
Universal serial interface (USI, 8-bit device) Available only in S1C17564
Power generator (VD1, 8-bit device) Available only in S1C17564
I/O port & port MUX (P, 8-bit device)
MISC register (MISC, 16-bit device)
IR remote controller (REMC, 16-bit device)
A/D converter (ADC10, 16-bit device)
16-bit PWM timers (T16A, 16-bit device)
Flash controller (FLASHC, 16-bit device)
S1C17 Core I/O Area
3.5
The 1K-byte area from address 0xfffc00 to address 0xffffff is the I/O area for the CPU core in which the I/O regis-
ters listed in the table below are located.
5.1 I/O Map (S1C17 Core I/O Area)
Table 3.
Peripheral
Address
Register name
Function
S1C17 Core I/O
0xffff84
IDIR
Processor ID Register
Indicates the processor ID.
0xffff90
DBRAM
Debug RAM Base Register
Indicates the debug RAM base address.
0xffffa0
DCR
Debug Control Register
Debug control
0xffffb4
IBAR1
Instruction Break Address Register 1
Instruction break address #1 setting
0xffffb8
IBAR2
Instruction Break Address Register 2
Instruction break address #2 setting
0xffffbc
IBAR3
Instruction Break Address Register 3
Instruction break address #3 setting
0xffffd0
IBAR4
Instruction Break Address Register 4
Instruction break address #4 setting
See “Processor Information” in the “CPU” chapter for more information on IDIR. See the “On-chip Debugger
(DBG)” chapter for more information on other registers.
This area includes the S1C17 Core registers, in addition to those described above. For more information on these
registers, refer to the “S1C17 Core Manual.”