15 UART
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
15-5
Data Transfer Control
15.5
Make the following settings before starting data transfers.
(1) Select the input clock. (See Section 15.3.)
(2) Program the baud rate generator to output the transfer clock. (See Section 15.3.)
(3) Set the transfer data format. (See Section 15.4.)
(4) To use the IrDA interface, set IrDA mode. (See Section 15.8.)
(5) Set interrupt conditions to use UART interrupts. (See Section 15.7.)
Note: Make sure the UART is halted (RXEN/UART_CTLx register = 0) before changing the above set-
tings.
Enabling data transfers
Set RXEN/UART_CTLx register to 1 to enable data transfers. This puts the transmitter/receiver circuit in ready-
to-transmit/receive status.
Note: Do not set RXEN to 0 while the UART is sending or receiving data.
Data transmission control
To start data transmission, write the transmit data to TXD[7:0]/UART_TXDx register.
The data is written to the transmit data buffer, and the transmitter circuit starts sending data.
The buffer data is sent to the transmit shift register, and the start bit is output from the SOUTx pin. The data in
the shift register is then output from the LSB. The transfer data bit is shifted in sync with the sampling clock
rising edge and output in sequence via the SOUTx pin. Following output of MSB, the parity bit (if parity is en-
abled) and the stop bit are output.
The transmitter circuit includes three status flags: TDBE/UART_STx register, TRBS/UART_STx register, and
TRED/UART_STx register.
The TDBE flag indicates the transmit data buffer status. This flag switches to 0 when the application program
writes data to the transmit data buffer and reverts to 1 when the buffer data is sent to the transmit shift register.
An interrupt can be generated when this flag is set to 1 (see Section 15.7). Subsequent data is sent after con-
firming that the transmit data buffer is empty either by using this interrupt or by reading the TDBE flag. The
transmit data buffer size is 1 byte, but a shift register is provided separately to allow data to be written while the
previous data is being sent. Always confirm that the transmit data buffer is empty before writing transmit data.
Writing data while the TDBE flag is 0 will overwrite earlier transmit data inside the transmit data buffer.
The TRBS flag indicates the shift register status. This flag switches to 1 when transmit data is loaded from the
transmit data buffer to the shift register and reverts to 0 once the data is sent. Read this flag to check whether
the transmitter circuit is operating or at standby.
The TRED switches to 1 when the TRBS flag reverts to 0 from 1, indicating that transmit operation has com-
pleted. An interrupt can be generated when this flag is set to 1 (see Section 15.7). Use this interrupt for trans-
mission end processing. The TRED flag is reset to 0 by writing 1.
S1: Start bit, S2: Stop bit, P: Parity bit, Wr: Data write to transmit data buffer
Sampling clock (sclk)
SOUTx
TDBE
TRBS
TRED
Interrupt
S1 D0 D1 D2 D3 D4 D5 D6 D7 P S2 S1 D0 D1
D7 P S2 S1 D0 D1
D7 P
Wr
S2
Transmit buffer empty interrupt request
End of transmission
interrupt request
5.1 Data Transmission Timing Chart
Figure 15.