18 I2C SLAVE (I2CS)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
18-9
Note: When the master device of the I2C bus, which has multiple slave devices connected includ-
ing this IC, starts communication with another slave device, the I2CS module issues NAK
in response to the sent slave address. On the other hand, the selected slave device issues
ACK. Therefore, DMS may be set due to a difference between the output value of this IC
and the SDA line status. When SELECTED/I2CS_ASTAT register is set to 0, you can ig-
nore DMS without a problem even if it is set to 1 as there is a difference in the response
code (ACK/NAK) from the selected slave device.
When the I2CS module is placed into asynchronous address detection mode (ASDET_EN
= 1), a DMS does not occur as in the condition above.
5. RXOVF/I2CS_STAT register: This bit is set to 1 when the next data has been received before the received
data is read (the received data is overwritten). (When the clock stretch function is disabled)
6. BFREQ/I2CS_STAT register: This bit is set to 1 when a bus free request is accepted.
7. DA_STOP/I2CS_STAT register: This bit is set to 1 if a stop condition is detected while this module is se-
lected as the slave device.
When one of the bits listed above is set to 1, BSTAT/I2CS_STAT register is set to 1 and an interrupt signal is
output to the ITC. An interrupt occurs if other interrupt conditions are satisfied. This interrupt can be used to
perform an error or terminate handling.
Set BSTAT_IEN/I2CS_ICTL register to 1 when using this interrupt. If BSTAT_IEN is set to 0 (default), inter-
rupt requests by this cause will not be sent to the ITC.
For more information on interrupt processing, see the “Interrupt Controller (ITC)” chapter.
Control Register Details
18.7
7.1 List of I2CS Registers
Table 18.
Address
Register name
Function
0x4360
I2CS_TRNS
I2C Slave Transmit Data Register
I2C slave transmit data
0x4362
I2CS_RECV
I2C Slave Receive Data Register
I2C slave receive data
0x4364
I2CS_SADRS I2C Slave Address Setup Register
Sets the I2C slave address.
0x4366
I2CS_CTL
I2C Slave Control Register
Controls the I2C slave module.
0x4368
I2CS_STAT
I2C Slave Status Register
Indicates the I2C bus status.
0x436a
I2CS_ASTAT
I2C Slave Access Status Register
Indicates the I2C slave access status.
0x436c
I2CS_ICTL
I2C Slave Interrupt Control Register
Controls the I2C slave interrupt.
The I2CS module registers are described in detail below. These are 16-bit registers.
Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.
I2C Slave Transmit Data Register (I2CS_TRNS)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
I2C Slave
Transmit Data
Register
(I2CS_TRNS)
0x4360
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 SDATA[7:0] I2C slave transmit data
0–0xff
0x0 R/W
D[15:8]
Reserved
D[7:0]
SDATA[7:0]: I2C Slave Transmit Data Bits
Sets a transmit data in this register. (Default: 0x0)
The serial-converted data is output from the SDA1 pin beginning with the MSB, in which the bits set to
0 are output as Low-level signals. When the data set in this register is sent to the shift register, a trans-
mit interrupt occurs. The next transmit data can be written to the register after that.
If the clock stretch function has been disabled, data must be written to this register within 7 cycles of
the I2C clock (SCL1 input clock) after a transmit interrupt has been occurred.
However, when setting the first transmit data after this module has been selected as the slave device,
follow the precautions described below.