APPENDIX A LIST OF I/O REGISTERS
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
AP-A-15
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
FOUTB Control
Register
(CLG_FOUTB)
S1C17554
0x5065
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–4 FOUTBD
[1:0]
FOUTB clock division ratio select
FOUTBD[1:0]
Division ratio
0x0 R/W When the clock
source is OSC3
0x3
0x2
0x1
0x0
reserved
1/4
1/2
1/1
D3–2 FOUTBSRC
[1:0]
FOUTB clock source select
FOUTBSRC[1:0] Clock source
0x0 R/W
0x3
0x2
0x1
0x0
reserved
OSC3
OSC1
reserved
D1
–
reserved
–
0 when being read.
D0
FOUTBE
FOUTB output enable
1 Enable
0 Disable
0
R/W
FOUTB Control
Register
(CLG_FOUTB)
S1C17564
0x5065
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–4 FOUTBD
[1:0]
FOUTB clock division ratio select
FOUTBD[1:0]
Division ratio
0x0 R/W When the clock
source is IOSC or
OSC3
0x3
0x2
0x1
0x0
reserved
1/4
1/2
1/1
D3–2 FOUTBSRC
[1:0]
FOUTB clock source select
FOUTBSRC[1:0] Clock source
0x0 R/W
0x3
0x2
0x1
0x0
reserved
OSC3
OSC1
IOSC
D1
–
reserved
–
0 when being read.
D0
FOUTBE
FOUTB output enable
1 Enable
0 Disable
0
R/W
IOSC Control
Register
(CLG_IOSC)
S1C17564
0x506e
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1–0 IOSCSEL
[1:0]
IOSC frequency select
IOSCSEL[1:0]
Frequency
0x1 R/W
0x3
0x2
0x1
0x0
2 MHz
4 MHz
12 MHz
8 MHz
PCLK Control
Register
(CLG_PCLK)
0x5080
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1–0 PCKEN[1:0] PCLK enable
PCKEN[1:0]
PCLK supply
0x3 R/W
0x3
0x2
0x1
0x0
Enable
Not allowed
Disable
CCLK Control
Register
(CLG_CCLK)
0x5081
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1–0 CCLKGR[1:0] CCLK clock gear ratio select
CCLKGR[1:0]
Gear ratio
0x0 R/W
0x3
0x2
0x1
0x0
1/8
1/4
1/2
1/1
0x50c0–0x50cf
USI Ch.0
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI Ch.0 Global
Configuration
Register
(USI_GCFG0)
0x50c0
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3
LSBFST
MSB/LSB first mode select
1 MSB first
0 LSB first
0
R/W
D2–0 USIMOD
[2:0]
Interface mode configuration
USIMOD[2:0]
I/F mode
0x0 R/W
0x7–0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
I2C slave
I2C master
reserved
SPI master
UART
Software reset
USI Ch.0
Transmit Data
Buffer Register
(USI_TD0)
0x50c1
(8 bits)
D7–0 TD[7:0]
USI transmit data buffer
TD7 = MSB
TD0 = LSB
0x0 to 0xff
0x0 R/W
USI Ch.0
Receive Data
Buffer Register
(USI_RD0)
0x50c2
(8 bits)
D7–0 RD[7:0]
USI receive data buffer
RD7 = MSB
RD0 = LSB
0x0 to 0xff
0x0
R
USI Ch.0
UART Mode
Configuration
Register
(USI_UCFG0)
0x50c3
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3
UCHLN
Character length select
1 8 bits
0 7 bits
0
R/W
D2
USTPB
Stop bit select
1 2 bits
0 1 bit
0
R/W
D1
UPMD
Parity mode select
1 Even
0 Odd
0
R/W
D0
UPREN
Parity enable
1 With parity
0 No parity
0
R/W
USI Ch.0 UART
Mode Interrupt
Enable Register
(USI_UIE0)
0x50c4
(8 bits)
D7–3 –
reserved
–
0 when being read.
D2
UEIE
Receive error interrupt enable
1 Enable
0 Disable
0
R/W
D1
URDIE
Receive buffer full interrupt enable 1 Enable
0 Disable
0
R/W
D0
UTDIE
Transmit buffer empty int. enable
1 Enable
0 Disable
0
R/W