17 I2C MASTER (I2CM)
17-4
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
Data reception control
The procedure for receiving data is described below. When receiving data, the slave address must be sent with
the transfer direction bit set to 1.
To receive data, set RXE/I2CM_DAT register to 1 for receiving 1 byte. When TXE/I2CM_DAT register is set
to 1 for sending the slave address, RXE can also be set to 1 at the same time. If both TXE and RXE are set to 1,
TXE takes priority.
When RXE is set to 1, allowing receiving to start, the I2CM module starts outputting the clock from the SCL0
pin with the SDA line at high impedance. The data is loaded to the shift register in sequence at the clock rising
edge, with the MSB leading.
RXE is reset to 0 when D6 is loaded.
The received data is loaded to RTDT[7:0] once the 8-bit data has been received in the shift register.
The I2CM module includes two status bits for receive control: RBRDY/I2CM_DAT register and RBUSY/
I2CM_CTL register.
The RBRDY flag indicates the received data status. This flag becomes 1 when the data received in the shift regis-
ter is loaded to RTDT[7:0] and reverts to 0 when the received data is read out from RTDT[7:0]. Interrupts can also
be generated once the flag value becomes 1.
The RBUSY flag indicates the receiving operation status. This flag is 1 when receiving starts and reverts to 0 when
the data is received. Inspect the flag to determine whether the I2CM module is currently receiving or in standby.
The I2CM module outputs 9 clocks with each data reception. In the 9th clock cycle, an ACK or NAK is sent to
the slave via the SDA0 pin. The bit state sent can be set in RTACK/I2CM_DAT register. To send ACK, set RT-
ACK to 0. To send NAK, set RTACK to 1.
End of data transfers (Generating stop condition)
To end data transfers after all data has been transferred, the I2C master (this module) must generate a stop con-
dition. The stop condition applies when the SCL line is maintained at High and the SDA line is pulled up from
Low to High.
SDA0 (output)
SCL0 (output)
Stop condition
5.4 Stop Condition
Figure 17.
The stop condition is generated by setting STP/I2CM_CTL register to 1.
When STP is set to 1, the I2CM module pulls up the I2C bus SDA line from Low to High with the SCL line
maintained at High to generates a stop condition. The I2C bus subsequently switches to free state.
Stop condition generation can be reserved. To reserve the stop condition, check that I2CM is operating (TBUSY
= 1 or RBUSY = 1), and then set STP to 1. The stop condition is generated as soon as data transfer (including
ACK transfer) ends. STP is reset to 0 when the stop condition is generated.
Continuing data transfer (Generating Repeated start condition)
To make it possible to continue with a different data transfer after data transfer completion, the I2C master (this
module) can generate a repeated start condition.
SDA0 (output)
SCL0 (output)
Repeated start condition
5.5 Repeated Start Condition
Figure 17.