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19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
19-26
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
URBSY is set to 1 when the first start bit is detected (when data reception begins) and is reset to 0 when
the data received in the shift register is loaded into the receive data buffer. Inspect URBSY to determine
whether the receiving circuit is operating or at standby.
D5
UTBSY: Transmit Busy Flag Bit
Indicates the transmit shift register status.
1 (R):
Busy
0 (R):
Idle (default)
UTBSY is set to 1 when transmit data is loaded from the transmit data buffer into the shift register and
is reset to 0 when the data transfer is completed. Inspect UTBSY to determine whether the transmit cir-
cuit is operating or at standby.
D4
UPEIF: Parity Error Flag Bit
Indicates whether a parity error has occurred or not.
1 (R):
Error occurred
0 (R):
No error (default)
1 (W):
Reset to 0
0 (W):
Ignored
UPEIF is set to 1 when a parity error occurs. At the same time a receive error interrupt request is sent
to the ITC if UEIE/USI_UIEx register is 1. Parity checking is enabled only when UPREN/USI_UCFGx
register is set to 1 and is performed when received data is transferred from the shift register to the
receive data buffer. UPEIF is reset by writing 1.
D3
USEIF: Framing Error Flag Bit
Indicates whether a framing error has occurred or not.
1 (R):
Error occurred
0 (R):
No error (default)
1 (W):
Reset to 0
0 (W):
Ignored
USEIF is set to 1 when a framing error occurs. At the same time a receive error interrupt request is sent
to the ITC if UEIE/USI_UIEx register is 1. A framing error occurs when data is received with the stop
bit set to 0. USEIF is reset by writing 1.
D2
UOEIF: Overrun Error Flag Bit
Indicates whether an overrun error has occurred or not.
1 (R):
Error occurred
0 (R):
No error (default)
1 (W):
Reset to 0
0 (W):
Ignored
UOEIF is set to 1 when an overrun error occurs. At the same time a receive error interrupt request is
sent to the ITC if UEIE/USI_UIEx register is 1. An overrun error occurs when the previous received
data in the receive data buffer before reading is overwritten with a new received data. UOEIF is reset by
writing 1.
D1
URDIF: Receive Buffer Full Flag Bit
Indicates the receive data buffer status.
1 (R):
Data full
0 (R):
No data (default)
1 (W):
Reset to 0
0 (W):
Ignored
URDIF is set to 1 when data received in the shift register is sent to the receive data buffer (when receiv-
ing is completed), indicating that the data can be read. At the same time a receive buffer full interrupt
request is sent to the ITC if URDIE/USI_UIEx register is 1. URDIF is reset by writing 1.