APPENDIX A LIST OF I/O REGISTERS
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
AP-A-11
0x4320–0x4326
SPI Ch.0
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
SPI Ch.0
Status Register
(SPI_ST0)
0x4320
(16 bits)
D15–3 –
reserved
–
0 when being read.
D2
SPBSY
Transfer busy flag (master)
1 Busy
0 Idle
0
R
ss signal low flag (slave)
1 ss = L
0 ss = H
D1
SPRBF
Receive data buffer full flag
1 Full
0 Not full
0
R
D0
SPTBE
Transmit data buffer empty flag
1 Empty
0 Not empty
1
R
SPI Ch.0
Transmit Data
Register
(SPI_TXD0)
0x4322
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 SPTDB[7:0] SPI transmit data buffer
SPTDB7 = MSB
SPTDB0 = LSB
0x0 to 0xff
0x0 R/W
SPI Ch.0
Receive Data
Register
(SPI_RXD0)
0x4324
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 SPRDB[7:0] SPI receive data buffer
SPRDB7 = MSB
SPRDB0 = LSB
0x0 to 0xff
0x0
R
SPI Ch.0
Control Register
(SPI_CTL0)
0x4326
(16 bits)
D15–10 –
reserved
–
0 when being read.
D9
MCLK
SPI clock source select
1 T16 Ch.1
0 PCLK/4
0
R/W
D8
MLSB
LSB/MSB first mode select
1 LSB
0 MSB
0
R/W
D7–6 –
reserved
–
0 when being read.
D5
SPRIE
Receive data buffer full int. enable 1 Enable
0 Disable
0
R/W
D4
SPTIE
Transmit data buffer empty int. enable 1 Enable
0 Disable
0
R/W
D3
CPHA
Clock phase select
1 Data out
0 Data in
0
R/W These bits must be
set before setting
SPEN to 1.
D2
CPOL
Clock polarity select
1 Active L
0 Active H
0
R/W
D1
MSSL
Master/slave mode select
1 Master
0 Slave
0
R/W
D0
SPEN
SPI enable
1 Enable
0 Disable
0
R/W
0x4340–0x4346
I2C Master
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
I2C Master
Enable Register
(I2CM_EN)
0x4340
(16 bits)
D15–1 –
reserved
–
0 when being read.
D0
I2CMEN
I2C master enable
1 Enable
0 Disable
0
R/W
I2C Master
Control Register
(I2CM_CTL)
0x4342
(16 bits)
D15–10 –
reserved
–
0 when being read.
D9
RBUSY
Receive busy flag
1 Busy
0 Idle
0
R
D8
TBUSY
Transmit busy flag
1 Busy
0 Idle
0
R
D7–5 –
reserved
–
0 when being read.
D4
NSERM
Noise remove on/off
1 On
0 Off
0
R/W
D3–2 –
reserved
–
0 when being read.
D1
STP
Stop control
1 Stop
0 Ignored
0
R/W
D0
STRT
Start control
1 Start
0 Ignored
0
R/W
I2C Master
Data Register
(I2CM_DAT)
0x4344
(16 bits)
D15–12 –
reserved
–
0 when being read.
D11
RBRDY
Receive buffer ready flag
1 Ready
0 Empty
0
R
D10
RXE
Receive execution
1 Receive
0 Ignored
0
R/W
D9
TXE
Transmit execution
1 Transmit
0 Ignored
0
R/W
D8
RTACK
Receive/transmit ACK
1 Error
0 ACK
0
R/W
D7–0 RTDT[7:0]
Receive/transmit data
RTDT7 = MSB
RTDT0 = LSB
0x0 to 0xff
0x0 R/W
I2C Master
Interrupt
Control Register
(I2CM_ICTL)
0x4346
(16 bits)
D15–2 –
reserved
–
0 when being read.
D1
RINTE
Receive interrupt enable
1 Enable
0 Disable
0
R/W
D0
TINTE
Transmit interrupt enable
1 Enable
0 Disable
0
R/W
0x4360–0x436c
I2C Slave
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
I2C Slave
Transmit Data
Register
(I2CS_TRNS)
0x4360
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 SDATA[7:0] I2C slave transmit data
0–0xff
0x0 R/W
I2C Slave
Receive Data
Register
(I2CS_RECV)
0x4362
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 RDATA[7:0] I2C slave receive data
0–0xff
0x0
R
I2C Slave
Address Setup
Register
(I2CS_SADRS)
0x4364
(16 bits)
D15–7 –
reserved
–
0 when being read.
D6–0 SADRS[6:0] I2C slave address
0–0x7f
0x0 R/W