15 UART
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
15-3
3.2 IOSC/OSC3 Division Ratio Selection
Table 15.
CLKDIV[1:0]
Division ratio
0x3
1/8
0x2
1/4
0x1
1/2
0x0
1/1
(Default: 0x0)
Clock supply to the counter is controlled using CLKEN/UART_CLKx register. The CLKEN default setting is 0,
which disables the clock supply. Setting CLKEN to 1 sends the clock selected to the counter.
Initial counter value setting
BR[7:0]/UART_BRx register is used to set the initial value for the down counter.
The initial counter value is preset to the down counter if the counter underflows. This means that the initial
counter value and the count clock frequency determine the time elapsed between underflows.
Underflow signal/
Baud rate generator output (sclk16)
Baud rate generator output (sclk)
123
816
3.2 Counter Underflow and Clock Generated
Figure 15.
Use the following equations to calculate the initial counter value for obtaining the desired transfer rate.
ct_clk
bps = ————————————
{(BR + 1)
× 16 + FMD}
ct_clk
BR =
(——— - FMD - 16) ÷ 16
bps
ct_clk: Count clock frequency (Hz)
BR:
BR[7:0] setting (0 to 255)
bps:
Transfer rate (bit/s)
FMD: FMD[3:0] (fine mode) setting (0 to 15)
Note: The UART transfer rate is capped at 960 kbps (115,200 bps in IrDA mode). Do not set faster
transfer rates.
Fine Mode
Fine mode provides a function that minimizes transfer rate errors. The baud rate generator output clock can be
set to the required frequency by selecting the appropriate clock source and initial counter data. Note that errors
may occur, depending on the transfer rate. Fine mode extends the output clock cycle by delaying the underflow
pulse from the counter. This delay can be specified with the FMD[3:0]/UART_FMDx register. FMD[3:0] speci-
fies the delay pattern to be inserted into a 16 underflow period. Inserting one delay extends the output clock
cycle by one count clock cycle.
3.3 Delay Patterns Specified by FMD[3:0]
Table 15.
FMD[3:0]
Underflow number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0x0
–
0x1
–
D
0x2
–
D
–
D
0x3
–
D
–
D
–
D
0x4
–
D
–
D
–
D
–
D
0x5
–
D
–
D
–
D
–
D
–
D
0x6
–
D
–
D
–
D
–
D
–
D
–
D
0x7
–
D
–
D
–
D
–
D
–
D
–
D
–
D
0x8
–
D
–
D
–
D
–
D
–
D
–
D
–
D
–
D
0x9
–
D
–
D
–
D
–
D
–
D
–
D
–
D
0xa
–
D
–
D
–
D
–
D
–
D
–
D
0xb
–
D
–
D
–
D
–
D
–
D
0xc
–
D
–
D
–
D
–
D
0xd
–
D
–
D
–
D
0xe
–
D
–
D
0xf
–
D
D: Indicates the insertion of a delay cycle.