![](http://datasheet.mmic.net.cn/120000/S1C17564F00E10C_datasheet_3574343/S1C17564F00E10C_247.png)
22 ON-CHIP DEBUGGER (DBG)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
22-1
On-chip Debugger (DBG)
22
Resource Requirements and Debugging Tools
22.1
Debugging work area
Debugging requires a 64-byte debugging work area. For more information on the work area location, see the
“Memory Map, Bus Control” chapter.
The start address for this debugging work area can be read from the DBRAM register (0xffff90).
Debugging tools
Debugging involves connecting ICDmini to the S1C17554/564 debug pins and inputting the debug instruction
from the debugger on the personal computer.
The following tools are required:
S1C17 Family In-Circuit Debugger ICDmini
S1C17 Family C compiler package (e.g., S5U1C17001C)
Debug pins
The following debug pins are used to connect ICDmini.
1.1 List of Debug Pins
Table 22.
Pin name
I/O
Qty
Function
DCLK
O
1
On-chip debugger clock output pin
Outputs a clock to the ICDmini.
DSIO
I/O
1
On-chip debugger data input/output pin
Used to input/output debugging data and input the break signal.
DST2
O
1
On-chip debugger status signal output pin
Outputs the processor status during debugging.
The on-chip debugger input/output pins (DCLK, DST2, DSIO) are shared with I/O ports and are initially set as
the debug pins. If the debugging function is not used, these pins can be switched using the port function select
bits to enable use as general-purpose I/O port pins.
For detailed information on pin function switching, see the “I/O Ports (P)” chapter.
Debug Break Operation Status
22.2
The S1C17 Core enters debug mode when the brk instruction is executed or a debug interrupt is generated by a
break signal (Low) input to the DSIO pin. This state persists until the retd instruction is executed. During this time,
hardware interrupts and NMIs are disabled.
The default setting halts peripheral circuit operations. This setting can be modified even when debugging is under-
way.
The peripheral circuits that operate with PCLK will continue running in debug mode by setting DBRUN1/MISC_
DMODE1 register to 1. Setting DBRUN1 to 0 (default) will stop these peripheral circuits in debug mode.
The peripheral circuits that operate with a clock other than PCLK will continue running in debug mode by setting
DBRUN2/MISC_DMODE2 register to 1. Setting DBRUN2 to 0 (default) will stop these peripheral circuits in de-
bug mode.
Some peripheral circuits, such as SPI, I2CS, and T16A, that run with an external input clock will not stop operating
even if the S1C17 Core enters debug mode.