APPENDIX A LIST OF I/O REGISTERS
AP-A-6
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
UART Ch.0
Mode Register
(UART_MOD0)
0x4103
(8 bits)
D7–5 –
reserved
–
0 when being read.
D4
CHLN
Character length select
1 8 bits
0 7 bits
0
R/W
D3
PREN
Parity enable
1 With parity
0 No parity
0
R/W
D2
PMD
Parity mode select
1 Odd
0 Even
0
R/W
D1
STPB
Stop bit select
1 2 bits
0 1 bit
0
R/W
D0
–
reserved
–
0 when being read.
UART Ch.0
Control Register
(UART_CTL0)
0x4104
(8 bits)
D7
TEIEN
End of transmission int. enable
1 Enable
0 Disable
0
R/W
D6
REIEN
Receive error int. enable
1 Enable
0 Disable
0
R/W
D5
RIEN
Receive buffer full int. enable
1 Enable
0 Disable
0
R/W
D4
TIEN
Transmit buffer empty int. enable
1 Enable
0 Disable
0
R/W
D3–2 –
reserved
–
0 when being read.
D1
RBFI
Receive buffer full int. condition setup 1 2 bytes
0 1 byte
0
R/W
D0
RXEN
UART enable
1 Enable
0 Disable
0
R/W
UART Ch.0
Expansion
Register
(UART_EXP0)
0x4105
(8 bits)
D7–1 –
reserved
–
0 when being read.
D0
IRMD
IrDA mode select
1 On
0 Off
0
R/W
UART Ch.0
Baud Rate
Register
(UART_BR0)
0x4106
(8 bits)
D7–0 BR[7:0]
Baud rate setting
0x0 to 0xff
0x0 R/W
UART Ch.0
Fine Mode
Register
(UART_FMD0)
0x4107
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3–0 FMD[3:0]
Fine mode setup
0x0 to 0xf
0x0 R/W Set a number of times
to insert delay into a
16-underflow period.
UART Ch.0
Clock Control
Register
(UART_CLK0)
0x506c
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–4 CLKDIV
[1:0]
Clock division ratio select
CLKDIV[1:0]
Division ratio
0x0 R/W When the clock
source is IOSC or
OSC3
0x3
0x2
0x1
0x0
1/8
1/4
1/2
1/1
D3–2 CLKSRC
[1:0]
Clock source select
CLKSRC[1:0]
Clock source
0x0 R/W
* S1C17564 only
0x3
0x2
0x1
0x0
External clock
OSC3
OSC1
IOSC*
D1
–
reserved
–
0 when being read.
D0
CLKEN
Count clock enable
1 Enable
0 Disable
0
R/W
0x4120–0x4127, 0x506d
UART (with IrDA) Ch.1
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
UART Ch.1
Status Register
(UART_ST1)
0x4120
(8 bits)
D7
TRED
End of transmission flag
1 Completed 0 Not completed
0
R/W Reset by writing 1.
D6
FER
Framing error flag
1 Error
0 Normal
0
R/W
D5
PER
Parity error flag
1 Error
0 Normal
0
R/W
D4
OER
Overrun error flag
1 Error
0 Normal
0
R/W
D3
RD2B
Second byte receive flag
1 Ready
0 Empty
0
R
D2
TRBS
Transmit busy flag
1 Busy
0 Idle
0
R Shift register status
D1
RDRY
Receive data ready flag
1 Ready
0 Empty
0
R
D0
TDBE
Transmit data buffer empty flag
1 Empty
0 Not empty
1
R
UART Ch.1
Transmit Data
Register
(UART_TXD1)
0x4121
(8 bits)
D7–0 TXD[7:0]
Transmit data
TXD7(6) = MSB
TXD0 = LSB
0x0 to 0xff (0x7f)
0x0 R/W
UART Ch.1
Receive Data
Register
(UART_RXD1)
0x4122
(8 bits)
D7–0 RXD[7:0]
Receive data in the receive data
buffer
RXD7(6) = MSB
RXD0 = LSB
0x0 to 0xff (0x7f)
0x0
R Older data in the buf-
fer is read out first.
UART Ch.1
Mode Register
(UART_MOD1)
0x4123
(8 bits)
D7–5 –
reserved
–
0 when being read.
D4
CHLN
Character length select
1 8 bits
0 7 bits
0
R/W
D3
PREN
Parity enable
1 With parity
0 No parity
0
R/W
D2
PMD
Parity mode select
1 Odd
0 Even
0
R/W
D1
STPB
Stop bit select
1 2 bits
0 1 bit
0
R/W
D0
–
reserved
–
0 when being read.
UART Ch.1
Control Register
(UART_CTL1)
0x4124
(8 bits)
D7
TEIEN
End of transmission int. enable
1 Enable
0 Disable
0
R/W
D6
REIEN
Receive error int. enable
1 Enable
0 Disable
0
R/W
D5
RIEN
Receive buffer full int. enable
1 Enable
0 Disable
0
R/W
D4
TIEN
Transmit buffer empty int. enable
1 Enable
0 Disable
0
R/W
D3–2 –
reserved
–
0 when being read.
D1
RBFI
Receive buffer full int. condition setup 1 2 bytes
0 1 byte
0
R/W
D0
RXEN
UART enable
1 Enable
0 Disable
0
R/W