8 I/O PORTS (P)
8-8
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
D[7:0]
PxOEN[7:0]: Px[7:0] Port Output Enable Bits
Enables or disables port outputs.
1 (R/W): Enabled
0 (R/W): Disabled (default)
PxOENy is the output enable bit that corresponds directly to Pxy port. Setting to 1 enables output and
the data set in PxOUTy is output from the port pin. Output is disabled when PxOENy is set to 0, and the
port pin is set into high-impedance status. The peripheral module determines whether output is enabled
or disabled when the port is used for a peripheral module function.
Refer to Table 8.3.1 for more information on input/output status for ports, including settings other than
for the PxOEN register.
Px Port Pull-up Control Registers (Px_PU)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Px Port Pull-up
Control Register
(Px_PU)
0x5203
0x5213
0x5223
0x5233
0x5243
0x5253
(8 bits)
D7–0 PxPU[7:0]
Px[7:0] port pull-up enable
1 Enable
0 Disable
1
(0xff)
R/W
Note: P0PU[3:0] only are available for the P0 ports. PxPU[5:0] only are available for the P4 and P5
ports. Other bits are reserved and always read as 0.
D[7:0]
PxPU[7:0]: Px[7:0] Port Pull-up Enable Bits
Enables or disables the pull-up resistor included in each port.
1 (R/W): Enabled (default)
0 (R/W): Disabled
PxPUy is the pull-up control bit that corresponds directly to the Pxy port. Setting to 1 enables the pull-
up resistor and the port pin will be pulled up when output is disabled (PxOENy = 0). When PxPUy is set
to 0, the pin will not be pulled up.
When output is enabled (PxOENy = 1), the PxPUy setting is ignored, and the pin is not pulled up.
I/O ports that are not used should be set with pull-up enabled.
This pull-up setting is also enabled for ports for which the peripheral module input function is selected.
Px Port Interrupt Mask Registers (Px_IMSK)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Px Port
Interrupt Mask
Register
(Px_IMSK)
0x5205
0x5215
0x5225
0x5235
0x5245
0x5255
(8 bits)
D7–0 PxIE[7:0]
Px[7:0] port interrupt enable
1 Enable
0 Disable
0
R/W
Note: P0IE[3:0] only are available for the P0 ports. PxIE[5:0] only are available for the P4 and P5 ports.
Other bits are reserved and always read as 0.
D[7:0]
PxIE[7:0]: Px[7:0] Port Interrupt Enable Bits
Enables or disables each port interrupt.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
Setting PxIEy to 1 enables the corresponding Pxy port input interrupt, while setting to 0 disables the in-
terrupt. Status changes for the input pins with interrupt disabled do not affect interrupt occurrence.