APPENDIX A LIST OF I/O REGISTERS
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
AP-A-3
Peripheral
Address
Register name
Function
USI Ch.0
(8-bit device)
0x50cb
USI_IMIE0
USI Ch.0 I2C Master Mode Interrupt Enable
Register
Enables interrupts.
0x50cc
USI_IMIF0
USI Ch.0 I2C Master Mode Interrupt Flag
Register
Indicates interrupt occurrence status.
0x50cd
USI_ISTG0
USI Ch.0 I2C Slave Mode Trigger Register
Starts I2C slave operations.
0x50ce
USI_ISIE0
USI Ch.0 I2C Slave Mode Interrupt Enable
Register
Enables interrupts.
0x50cf
USI_ISIF0
USI Ch.0 I2C Slave Mode Interrupt Flag Register Indicates interrupt occurrence status.
USI Ch.1
(8-bit device)
0x50e0
USI_GCFG1
USI Ch.1 Global Configuration Register
Sets interface and MSB/LSB mode.
0x50e1
USI_TD1
USI Ch.1 Transmit Data Buffer Register
Transmit data buffer
0x50e2
USI_RD1
USI Ch.1 Receive Data Buffer Register
Receive data buffer
0x50e3
USI_UCFG1
USI Ch.1 UART Mode Configuration Register
Sets UART transfer conditions.
0x50e4
USI_UIE1
USI Ch.1 UART Mode Interrupt Enable Register Enables interrupts.
0x50e5
USI_UIF1
USI Ch.1 UART Mode Interrupt Flag Register
Indicates interrupt occurrence status.
0x50e6
USI_SCFG1
USI Ch.1 SPI Master Mode Configuration
Register
Sets SPI transfer conditions.
0x50e7
USI_SIE1
USI Ch.1 SPI Master Mode Interrupt Enable
Register
Enables interrupts.
0x50e8
USI_SIF1
USI Ch.1 SPI Master Mode Interrupt Flag
Register
Indicates interrupt occurrence status.
0x50e9
USI_SMSK1
USI Ch.1 SPI Master Mode Receive Data Mask
Register
Sets receive data mask.
0x50ea
USI_IMTG1
USI Ch.1 I2C Master Mode Trigger Register
Starts I2C master operations.
0x50eb
USI_IMIE1
USI Ch.1 I2C Master Mode Interrupt Enable
Register
Enables interrupts.
0x50ec
USI_IMIF1
USI Ch.1 I2C Master Mode Interrupt Flag
Register
Indicates interrupt occurrence status.
0x50ed
USI_ISTG1
USI Ch.1 I2C Slave Mode Trigger Register
Starts I2C slave operations.
0x50ee
USI_ISIE1
USI Ch.1 I2C Slave Mode Interrupt Enable
Register
Enables interrupts.
0x50ef
USI_ISIF1
USI Ch.1 I2C Slave Mode Interrupt Flag Register Indicates interrupt occurrence status.
Power
generator
(8-bit device)
0x5121
VD1_CTL
VD1 Control Register
Controls the regulator operation mode.
P port &
port MUX
(8-bit device)
0x5200
P0_IN
P0 Port Input Data Register
P0 port input data
0x5201
P0_OUT
P0 Port Output Data Register
P0 port output data
0x5202
P0_OEN
P0 Port Output Enable Register
Enables P0 port outputs.
0x5203
P0_PU
P0 Port Pull-up Control Register
Controls the P0 port pull-up resistor.
0x5205
P0_IMSK
P0 Port Interrupt Mask Register
Enables P0 port interrupts.
0x5206
P0_EDGE
P0 Port Interrupt Edge Select Register
Selects the signal edge for generating P0
port interrupts.
0x5207
P0_IFLG
P0 Port Interrupt Flag Register
Indicates/resets the P0 port interrupt occur-
rence status.
0x5208
P0_CHAT
P0 Port Chattering Filter Control Register
Controls the P0 port chattering filter.
0x5209
P0_KRST
P0 Port Key-Entry Reset Configuration Register Configures the P0 port key-entry reset function.
0x520a
P0_IEN
P0 Port Input Enable Register
Enables P0 port inputs.
0x5210
P1_IN
P1 Port Input Data Register
P1 port input data
0x5211
P1_OUT
P1 Port Output Data Register
P1 port output data
0x5212
P1_OEN
P1 Port Output Enable Register
Enables P1 port outputs.
0x5213
P1_PU
P1 Port Pull-up Control Register
Controls the P1 port pull-up resistor.
0x5215
P1_IMSK
P1 Port Interrupt Mask Register
Enables P1 port interrupts.
0x5216
P1_EDGE
P1 Port Interrupt Edge Select Register
Selects the signal edge for generating P1
port interrupts.
0x5217
P1_IFLG
P1 Port Interrupt Flag Register
Indicates/resets the P1 port interrupt occur-
rence status.
0x5218
P1_CHAT
P1 Port Chattering Filter Control Register
Controls the P1 port chattering filter.
0x521a
P1_IEN
P1 Port Input Enable Register
Enables P1 port inputs.
0x5220
P2_IN
P2 Port Input Data Register
P2 port input data
0x5221
P2_OUT
P2 Port Output Data Register
P2 port output data
0x5222
P2_OEN
P2 Output Enable Register
Enables P2 port outputs.
0x5223
P2_PU
P2 Port Pull-up Control Register
Controls the P2 port pull-up resistor.
0x5225
P2_IMSK
P2 Port Interrupt Mask Register
Enables P2 port interrupts.
0x5226
P2_EDGE
P2 Port Interrupt Edge Select Register
Selects the signal edge for generating P2
port interrupts.
0x5227
P2_IFLG
P2 Port Interrupt Flag Register
Indicates/resets the P2 port interrupt occur-
rence status.
0x5228
P2_CHAT
P2 Port Chattering Filter Control Register
Controls the P2 port chattering filter.
0x522a
P2_IEN
P2 Port Input Enable Register
Enables P2 port inputs.
0x5230
P3_IN
P3 Port Input Data Register
P3 port input data
0x5231
P3_OUT
P3 Port Output Data Register
P3 port output data