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APPENDIX A LIST OF I/O REGISTERS
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
AP-A-7
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
UART Ch.1
Expansion
Register
(UART_EXP1)
0x4125
(8 bits)
D7–1 –
reserved
–
0 when being read.
D0
IRMD
IrDA mode select
1 On
0 Off
0
R/W
UART Ch.1
Baud Rate
Register
(UART_BR1)
0x4126
(8 bits)
D7–0 BR[7:0]
Baud rate setting
0x0 to 0xff
0x0 R/W
UART Ch.1
Fine Mode
Register
(UART_FMD1)
0x4127
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3–0 FMD[3:0]
Fine mode setup
0x0 to 0xf
0x0 R/W Set a number of times
to insert delay into a
16-underflow period.
UART Ch.1
Clock Control
Register
(UART_CLK1)
0x506d
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–4 CLKDIV
[1:0]
Clock division ratio select
CLKDIV[1:0]
Division ratio
0x0 R/W When the clock
source is IOSC or
OSC3
0x3
0x2
0x1
0x0
1/8
1/4
1/2
1/1
D3–2 CLKSRC
[1:0]
Clock source select
CLKSRC[1:0]
Clock source
0x0 R/W
* S1C17564 only
0x3
0x2
0x1
0x0
External clock
OSC3
OSC1
IOSC*
D1
–
reserved
–
0 when being read.
D0
CLKEN
Count clock enable
1 Enable
0 Disable
0
R/W
0x4200–0x4208
Fine Mode 16-bit Timer Ch.0
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
T16F Ch.0
Count Clock
Select Register
(T16F_CLK0)
0x4200
(16 bits)
D15–4 –
reserved
–
0 when being read.
D3–0 DF[3:0]
Count clock division ratio select
DF[3:0]
Division ratio
0x0 R/W Source clock = PCLK
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
T16F Ch.0
Reload Data
Register
(T16F_TR0)
0x4202
(16 bits)
D15–0 TR[15:0]
Reload data
TR15 = MSB
TR0 = LSB
0x0 to 0xffff
0x0 R/W
T16F Ch.0
Counter Data
Register
(T16F_TC0)
0x4204
(16 bits)
D15–0 TC[15:0]
Counter data
TC15 = MSB
TC0 = LSB
0x0 to 0xffff
0xffff
R
T16F Ch.0
Control Register
(T16F_CTL0)
0x4206
(16 bits)
D15–12 –
reserved
–
0 when being read.
D11–8 TFMD[3:0] Fine mode setup
0x0 to 0xf
0x0 R/W Set a number of times
to insert delay into a
16-underflow period.
D7–5 –
reserved
–
0 when being read.
D4
TRMD
Count mode select
1 One shot
0 Repeat
0
R/W
D3–2 –
reserved
–
0 when being read.
D1
PRESER
Timer reset
1 Reset
0 Ignored
0
W
D0
PRUN
Timer run/stop control
1 Run
0 Stop
0
R/W
T16F Ch.0
Interrupt
Control Register
(T16F_INT0)
0x4208
(16 bits)
D15–9 –
reserved
–
0 when being read.
D8
T16FIE
T16F interrupt enable
1 Enable
0 Disable
0
R/W
D7–1 –
reserved
–
0 when being read.
D0
T16FIF
T16F interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.