![](http://datasheet.mmic.net.cn/120000/S1C17564F00E10C_datasheet_3574343/S1C17564F00E10C_208.png)
19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
19-21
Receive buffer full interrupt
To use this interrupt, set SRDIE/USI_SIEx register to 1. If SRDIE is set to 0 (default), interrupt requests for this
cause will not be sent to the ITC.
If a received data is loaded into the receive data buffer, the USI module sets SRDIF/USI_SIFx register to 1. If
receive buffer full interrupts are enabled (SRDIE = 1), an interrupt request is sent simultaneously to the ITC. An
interrupt occurs if other interrupt conditions are met. You can inspect the SRDIF flag in the interrupt handler
routine to determine whether the USI (SPI master mode) interrupt is attributable to a receive buffer full. If SR-
DIF is 1, the received data can be read from the receive data buffer by the interrupt handler routine. However,
be sure to check whether a receive error has occurred or not.
Receive error interrupt
To use this interrupt, set SEIE/USI_SIEx register to 1. If SEIE is set to 0 (default), interrupt requests for this
cause will not be sent to the ITC.
The USI module sets SEIF/USI_SIFx register to 1 if an overrun error is detected when receiving data. If receive
error interrupts are enabled (SEIE = 1), an interrupt request is sent simultaneously to the ITC. An interrupt oc-
curs if other interrupt conditions are met. You can inspect the SEIF flags in the interrupt handler routine to de-
termine whether the USI (SPI master mode) interrupt was caused by a receive error. If SEIF is 1, the interrupt
handler routine will proceed with error recovery.
Interrupts in I
19.7.3
2C Master Mode
The I2C master mode includes a function for generating the following two different types of interrupts.
Operation completion interrupt
Receive error interrupt
Operation completion interrupt
To use this interrupt, set IMIE/USI_IMIEx register to 1. If IMIE is set to 0 (default), interrupt requests for this
cause will not be sent to the ITC.
When the operation that initiated by a software trigger has completed, the USI module sets IMIF/USI_IMIFx
register to 1. If operation completion interrupts are enabled (IMIE = 1), an interrupt request is sent simultane-
ously to the ITC. An interrupt occurs if other interrupt conditions are met. You can inspect the IMSTA[2:0]/
USI_IMIFx register in the interrupt handler routine to determine the I2C operation/status that causes the inter-
rupt.
7.3.1 I
Table 19.
2C Master Status Bits
IMSTA[2:0]
Status
0x7
Reserved
0x6
NAK has been received.
0x5
ACK has been received.
0x4
ACK or NAK has been transmitted.
0x3
Receive data buffer is full.
0x2
Transmit data buffer is empty.
0x1
Stop condition has been generated.
0x0
Start condition has been generated.
(Default: 0x0)
Receive error interrupt
To use this interrupt, set IMEIE/USI_IMIEx register to 1. If IMEIE is set to 0 (default), interrupt requests for
this cause will not be sent to the ITC.
The USI module sets IMEIF/USI_IMIFx register to 1 if an overrun error is detected when receiving data. If
receive error interrupts are enabled (IMEIE = 1), an interrupt request is sent simultaneously to the ITC. An
interrupt occurs if other interrupt conditions are met. You can inspect the IMEIF flags in the interrupt handler
routine to determine whether the USI (I2C master mode) interrupt was caused by a receive error. If IMEIF is 1,
the interrupt handler routine will proceed with error recovery.