19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
19-16
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
US_SCKx pin (input)
US_SCKx pin (output)
US_SDIx pin (input)
US_SDIx pin (output)
ISTGMOD[2:0]
ISTG (write)
ISBSY
ISSTA[2:0]
TD[7:0]
ISIF
Interrupt
A6
Transfer data 1
0x0
0x3
0x2
0x4
0x2
0x6
Transfer data 2
0x3
A5
A4
A3
A2
A1
A0
R/W = 1
ACK
Start
condition
Slave address reception
Data transmission
Start condition
detected
ACK
sent
Receive
buffer full
Transmit
buffer empty
* Reset by writing 1
*
0x0
D7
D6
(1) Start condition
→ Data transmission
0x6
0x2
Transfer data (n -1)
0x2
0x5
0x6
0x2
0x6
0x0
0x1
Transfer data n
ACK received Transmit buffer empty
Stop condition
detected
NAK
received
*
* Reset by writing 1
D5
D4
D3
D2
D1
D0
D7
D6
D0
ACK
US_SCKx pin (input)
US_SCKx pin (output)
US_SDIx pin (input)
US_SDIx pin (output)
ISTGMOD[2:0]
ISTG (write)
ISBSY
ISSTA[2:0]
TD[7:0]
ISIF
Interrupt
Data transmission
Stop
condition
NAK
(2) Data transmission
→ Stop condition
5.3.12 I
Figure 19.
2C Slave Data Transmission Timing Chart
Note: The timing chart above shows a basic transfer operation that does not include an actual I2C trans-
fer procedure. See “Receiving control byte in I2C slave mode” in “19.9 Precautions.”
(1) Waiting for start condition
I2C data transfer starts when the I2C master device generates a start condition (see Figure 19.5.3.3).
First enable this I2C slave to detect a start condition by setting ISTGMOD[2:0] to 0x0 (default) and writing
1 to ISTG. The I2C controller starts detecting a start condition and sets ISBSY to 1. ISBSY is set to 1 while
a start condition is being detected. ISBSY reverts to 0 and ISSTA[2:0] is set to 0x0 when the detection has
completed. Check if a start condition is generated by reading ISBSY or using an interrupt.
Note: Other operations cannot be started before a start condition is detected.
(2) Receiving slave address and transfer direction data bit
The I2C master sends the address of the slave device to be communicated and a transfer direction bit (see
Figure 19.5.3.4) after it has generated a start condition. Set this I2C slave into receiving status to receive the
slave address. To start reception, set ISTGMOD[2:0] to 0x3 and write 1 to ISTG.
This trigger starts sampling clocks input from the US_SCKx pin. When clocks are input, the I2C controller
loads the US_SDOx pin status to the shift register in sync with each clock. The received data is loaded to
the receive data buffer (RD[7:0]/USI_RDx register) once the 8-bit data has been received in the shift regis-
ter.
Writing 1 to ISTG sets ISBSY to 1. When the received data is loaded to the receive data buffer, ISBSY
reverts to 0 and ISSTA[2:0] is set to 0x3 (receive data buffer full). An interrupt request can be generated at
this point. Read the received data from the receive data buffer using this interrupt.
When a 7-bit address is used, the slave address and transfer direction bit can be obtained in one operation.
When a 10-bit address is used, save the first data received in the receive data buffer into the memory and
perform data reception again to obtain the remaining address bits.