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8 I/O PORTS (P)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
8-9
Px Port Interrupt Edge Select Registers (Px_EDGE)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Px Port
Interrupt Edge
Select Register
(Px_EDGE)
0x5206
0x5216
0x5226
0x5236
0x5246
0x5256
(8 bits)
D7–0 PxEDGE[7:0] Px[7:0] port interrupt edge select
1 Falling edge 0 Rising edge
0
R/W
Note: P0EDGE[3:0] only are available for the P0 ports. PxEDGE[5:0] only are available for the P4 and
P5 ports. Other bits are reserved and always read as 0.
D[7:0]
PxEDGE[7:0]: Px[7:0] Port Interrupt Edge Select Bits
Selects the input signal edge for generating each port interrupt.
1 (R/W): Falling edge
0 (R/W): Rising edge (default)
Port interrupts are generated at the input signal falling edge when PxEDGEy is set to 1 and at the rising
edge when set to 0.
Px Port Interrupt Flag Registers (Px_IFLG)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Px Port
Interrupt Flag
Register
(Px_IFLG)
0x5207
0x5217
0x5227
0x5237
0x5247
0x5257
(8 bits)
D7–0 PxIF[7:0]
Px[7:0] port interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
Note: P0IF[3:0] only are available for the P0 ports. PxIF[5:0] only are available for the P4 and P5 ports.
Other bits are reserved and always read as 0.
D[7:0]
PxIF[7:0]: Px[7:0] Port Interrupt Flag Bits
These are interrupt flags indicating the interrupt cause occurrence status.
1 (R):
Interrupt cause occurred
0 (R):
No interrupt cause occurred (default)
1 (W):
Reset flag
0 (W):
Ignored
PxIFy is the interrupt flag that corresponds directly to the Pxy port and is set to 1 at the specified edge
(rising or falling edge) of the input signal. When the corresponding PxIEy/Px_IMSK register has been
set to 1, a port interrupt request signal is also output to the ITC at the same time. An interrupt is gener-
ated if the ITC and S1C17 Core interrupt conditions are satisfied.
PxIFy is reset by writing 1.
Notes: The P port module interrupt flag PxIFy must be reset in the interrupt handler routine after a
port interrupt has occurred to prevent recurring interrupts.
To prevent generating unnecessary interrupts, reset the relevant PxIFy before enabling in-
terrupts for the required port using PxIEy/Px_IMSK register.