6 INTERRUPT CONTROLLER (ITC)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
6-1
Interrupt Controller (ITC)
6
ITC Module Overview
6.1
The interrupt controller (ITC) honors interrupt requests from the peripheral modules and outputs the interrupt re-
quest, interrupt level and vector number signals to the S1C17 Core according to the priority and interrupt levels.
The features of the ITC module are listed below.
Supports 23 maskable interrupt systems (for 26 interrupt sources listed below).
1. P00–P03 input interrupt (4 types)
2. P10–P17 input interrupt (8 types)
3. P20–P27 input interrupt (8 types)
4. P30–P37 input interrupt (8 types)
5. P40–P45 input interrupt (6 types)
6. P50–P55 input interrupt (6 types)
* Cannot be used in the S1C17554 WCSP-48 package.
7. Stopwatch timer interrupt (3 types)
8. Clock timer interrupt (4 types)
9. 16-bit PWM timer Ch.0 interrupt (6 types)
10. 16-bit PWM timer Ch.1 interrupt (6 types)
11. 16-bit PWM timer Ch.2 interrupt (6 types)
12. 16-bit PWM timer Ch.3 interrupt (6 types)
13. Fine mode 16-bit timer Ch.0 & Ch.1 interrupt (2 types)
14. 16-bit timer Ch.0 interrupt (1 type)
15. 16-bit timer Ch.1 interrupt (1 type)
16. 16-bit timer Ch.2 interrupt (1 type)
17. USI Ch.0 & Ch.1 interrupt (6 types)
* Cannot be used in the S1C17554.
18. UART Ch.0 interrupt (4 types)
19. UART Ch.1 interrupt (4 types)
20. IR remote controller interrupt (3 types)
21. SPI Ch.0 interrupt (2 types)
22. SPI Ch.1 interrupt (2 types)
23. SPI Ch.2 interrupt (2 types)
24. I2C master interrupt (2 types)
25. I2C slave interrupt (3 types)
26. A/D converter interrupt (2 types)
Supports eight interrupt levels to prioritize the interrupt sources.
The ITC enables the interrupt level (priority) for determining the processing sequence when multiple interrupts oc-
cur simultaneously to be set for each interrupt system separately.
Each interrupt system includes the number of interrupt causes indicated in parentheses above. Settings to enable or
disable interrupt for different causes are set by the respective peripheral module registers.
For specific information on interrupt causes and their control, refer to the peripheral module explanations.
Figure 6.1.1 shows the structure of the interrupt system.