17 I2C MASTER (I2CM)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
17-3
Slave address
7-bit address
Transfer direction
0: master
→ slave (transmission)
1: slave
→ master (reception)
A6
A5
D7
D6
A4
D5
A3
D4
A2
D3
A1
D2
A0
D1
DIR
D0
8 low order slave address bits
A7
A6
D7
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
2 high order
slave address bits
10-bit address
Transfer direction
0: master
→ slave (transmission)
1: slave
→ master (reception)
1
First transmit data
Second transmit data
1
D7
D6
1
D5
1
D4
0
D3
A9
D2
A8
D1
DIR
D0
5.2 Transmit Data Specifying Slave Address and Transfer Direction
Figure 17.
The transfer direction bit indicates the data transfer direction after the slave address has been sent. This is set to
0 when sending data from the master to the slave and to 1 when receiving data from the slave. To send a slave
address, set the address with the transfer direction bit to RTDT[7:0]/I2CM_DAT register. At the same time, set
TXE/I2CM_DAT register transmitting the address to 1.
After the slave address has been output, data can be sent and received as many times as required. Data must be
sent or received according to the transfer direction set together with the slave address.
Data transmission control
The procedure for transmitting data is described below. Data transmission is performed by the same procedure
as for slave address transmission.
To send byte data, set the transmit data to RTDT[7:0] and set TXE to 1 to transmit 1 byte.
When TXE is set to 1, the I2CM module begins data transmission in sync with the clock. If the previous data
is currently being transmitted, data transmission starts after this has been completed. The I2CM module first
transfers the data written to the shift register, then starts outputting the clock from the SCL0 pin. TXE is reset to
0 at this point and a cause of interrupt occurs, enabling the subsequent transmission data and TXE to be set.
The data bits in the shift register are shifted in sequence at the clock falling edge and output via the SDA0 pin
with the MSB leading. The I2CM module outputs 9 clocks with each data transmission. In the 9th clock cycle,
the I2CM module sets the SDA line into high impedance to receive an ACK or NAK sent from the slave device.
The slave device returns ACK (0) to the master if the data is received. If the data is not received, the SDA line is
not pulled down, which the I2CM module interprets to mean a NAK (1) (transmission failed).
SDA0 (output)
SDA0 (input)
SCL0 (output)
Start condition
12
89
D7
D6
D0
ACK
NAK
5.3 ACK and NAK
Figure 17.
The I2CM module includes two status bits for transmission control: TBUSY/I2CM_CTL register and RTACK/
I2CM_DAT register.
The TBUSY flag indicates the data transmission status. This flag becomes 1 when transmission starts (including
slave address transmission) and reverts to 0 once data transmission ends. Inspect the flag to check whether the
I2CM module is currently transmitting or at standby.
The RTACK bit indicates whether or not the slave device returned an ACK for the previous transmission. RT-
ACK is 0 if an ACK was returned and 1 if ACK was not returned.