AMD Alchemy Au1550 Security Network Processor Data Book
195
Security Engine
30283D
7.4.1.4
Packet Engine DMA Burst Transfer Size Register
The DMA burst transfer size register is used to specify the maximum burst transfer size.
7.4.1.5
Endian Configuration Register
The endian configuration register (sec_endian) allows byte swapping for transfers across the security engine system inter-
face. Separate controls are provided for host-initiated transfers (SBLn) and packet-engine-initiated transfers (MBLn).
The endian handler can be selectively enabled depending on the type of data being transferred. Individual endian swap
tors, SA records, and packet data.
Accesses to the internal registers (except sec_endian) and memory space of the security engine pass through the endian
handler.
19
MTA
Master Transfer Active. A ‘1’ indicates that a DMA transfer is active.
R
0
18:12
—
Reserved.
R
all 0s
11:0
TLEN
Transfer Length. Shows the data length, in bytes, for the DMA transaction.
Valid values range from 1 to 4095 bytes.
Rall 0s
sec_dmaburst
Offset = 0x00D4
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
MAX TSIZE
Def. 00000000000000000000000000100000
Bits
Name
Description
R/W
Default
31:12
—
Reserved.
R/W
all 0s
11:2
MAX TSIZE
Maximum Transfer Size. This specifies the largest packet engine transfers
(in words) that the DMA engine will perform. Requested transfers larger
than this size are broken into multiple burst transfers of this size or less.
R/W
0x8
1:0
—
Reserved.
R/W
00
sec_dmaendian
Offset = 0x00E0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
SBL3
SBL2
SBL1
SBL0
MBL3
MBL2
MBL1
MBL0
Def. 00000000111001000000000011100100
Bits
Name
Description
R/W
Default
31:24
—
Reserved
R/W
0
23:16
SBL3, SBL2,
SBL1, SBL0
Host transfers. Byte lane sources for byte n. Default is no swap (direct
pass).
00
Use byte lane 0 as the source.
01
Use byte lane 1 as the source.
10
Use byte lane 2 as the source.
11
Use byte lane 3 as the source.
R/W
0xE4
15:8
—
Reserved.
R/W
0
7:0
MBL3, MBL2,
MBL1, MBL0
Packet engine transfers. Byte lane sources for byte n. Default is no swap
(direct pass).
00
Use byte lane 0 as the source.
01
Use byte lane 1 as the source.
10
Use byte lane 2 as the source.
11
Use byte lane 3 as the source.
R/W
0xE4
Bits
Name
Description
R/W
Default