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AMD Alchemy Au1550 Security Network Processor Data Book
AC97 Controller
30283D
8.4.1.5
AC97 Event Register
The AC97 event register (psc_ac97evnt) contains the AC97 event flags. When an event flag is set, the event generates an
interrupt unless masked in the AC97 mask register (psc_ac97msk).
Once software detects an interrupt, software must read psc_ac97evnt to determine the interrupt source. Once the event
has been read, software must clear it so that the next event is not missed.
Once an event flag has been set, it remains set until cleared by software. A flag is cleared by writing a 1 to the appropriate
bit; writing a 0 has no effect.
5
RB
Receive Busy. Indicates the receive controller is enabled and is receiving
data.
R0
4
TB
Transmit Busy. Indicates the transmit controller is enabled and is transmit-
ting data.
R0
3
-
Reserved.
-
0
2
DI
Device Interrupt. Indicates at least one unmasked event has been flagged
in psc_ac97evnt.
R0
1
DR
Device Ready. Indicates the AC97 controller is ready for protocol operation
after setting the device-enable bit psc_ac97cfg[DE].
R0
0
SR
PSC Ready. Indicates the PSC is ready for protocol configuration after
enabling the PSC in psc_ctrl[ENA].
R0
psc_ac97evnt
Offset = 0x0018
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
GR CD
RR RO RU TR TO TU
RD TD
Def. 00000000000000000000000000000000
Bits
Name
Description
R/W
Default
31:26
-
Reserved.
-
0
25
GR
GPI Data Ready. Indicates new data is ready in the GPIO Input register.
(Only used when the GPIO registers are enabled.)
R/W
0
24
CD
Codec Command Done. Indicates a Codec Command has successfully
completed.
R/W
0
23:14
-
Reserved.
-
0
13
RR
Receive Request. Applies to programmed I/O only (psc_ac97cfg[DD]=1).
Indicates the Rx FIFO has a number of data elements equal to the FIFO
threshold programmed in psc_ac97cfg[RT] available for reading.
R/W
0
12
RO
Receive Overflow. Indicates the Rx FIFO has experienced an overflow.
R/W
0
11
RU
Receive Underflow. Indicates the Rx FIFO has experienced an underflow.
R/W
0
10
TR
Transmit Request. Applies to programmed I/O only (psc_ac97cfg[DD]=1).
Indicates the Tx FIFO is requesting a number of data elements equal to
the FIFO threshold programmed in psc_ac97cfg[TT].
R/W
0
9
TO
Transmit Overflow. Indicates the Tx FIFO has experienced an overflow.
R/W
0
8
TU
Transmit Underflow. Indicates the Tx FIFO has experienced an underflow.
R/W
0
7:6
-
Reserved.
-
0
5
RD
Receive Done. This flag is to indicate that the receive controller has been
disabled.
R/W
0
4
TD
Transmit Done. This flag is set to indicate that all data has been transmit-
ted and the transmit controller has been disabled.
R/W
0
3:0
-
Reserved.
-
0
Bits
Name
Description
R/W
Default