AMD Alchemy Au1550 Security Network Processor Data Book
379
EJTAG Implementation
30283D
12.4.2.4
Address Register
The read-only Address register provides the address for a processor access. The width of the register is 36 bits.
The value read in the register is valid if a processor access is pending; otherwise, the value is undefined. The two least-sig-
nificant bits of the register are used with the Psz field from the EJTAG Control register to indicate the size and data position
of the pending processor access transfer. These bits are not taken directly from the address referenced by the load/store
(i.e., these bits are encoded with Psz).
12.4.2.5
EJTAG Control Register (ECR)
The 32-bit EJTAG Control Register (ECR) handles processor reset, Debug Mode indication, access start, finish, and size
and read/write indication. The ECR also:
Controls debug vector location and indication of serviced processor accesses.
Allows debug interrupt request.
Indicates processor low-power mode.
The EJTAG Control register is not updated/written in the Update-DR state unless the Reset occurred; that is RO (bit 31) is
either already 0 or is written to 0 at the same time. This condition ensures proper handling of processor accesses after a
reset.
Bits that are R/W in the register return their written value on a subsequent read, unless other behavior is defined. Internal
synchronization hardware thus ensures that a written value is updated for reading immediately afterwards, even when the
TAP controller takes the shortest path from the Update-DR to Capture-DR state.
Note: To ensure a write is successful to the PE, PT and EB bits when the processor is undergoing a clock change (for PLL
lock/relock), the host must continue writing these bits until the write is verified by reading the change. Failure to do this
could result in the write of these bits being lost.
Reset of the processor can be indicated in the TCK domain a number of TCK cycles after it is removed in the processor
clock domain in order to allow for proper synchronization between the two clock domains.
ADDRESS
TAP Instruction ADDRESS or ALL
Bit 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
ADDRESS
Def XXXX
XXXXXXXXXXXXXX
XXXX
Bits
Name
Description
R/W
Default
35:0
ADDRESS[35:0]
Address used by processor access
R
UNPRED
ECR
TAP Instruction CONTROL or ALL
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
RO
PSZ
DZ
PRW PA
PR PE PT
EB
DM
Def. 1
x
000000000
x
0000000000000000000
Bits
Name
Description
R/W
Default
31
RO
Indicates if a processor reset has occurred since the bit was cleared:
0
No reset occurred
1
Reset occurred
The RO bit stays set as long as reset is applied.
This bit must be cleared to acknowledge that the reset was detected. The
EJTAG Control register is not updated in the Update-DR state unless RO
is 0 or written to 0 at the same time. This is in order to ensure correct han-
dling of the processor access after reset.
R/W0
1