20
AMD Alchemy Au1550 Security Network Processor Data Book
Au1 Core and System Bus
30283D
A cache line is tagged with a 20-bit physical address, a lock bit, and a valid bit. Data cache lines also include coherency and
dirty status bits. The physical address tag contains bits 31:12 of the physical address; as such, physical addresses in which
bits [35:32] are non-zero are not cacheable.
A cache line address is always 32-byte aligned. The cache is indexed with the lower, untranslated bits (bits 11:5) of the vir-
tual address, allowing the virtual-to-physical address translation and the cache access to occur in parallel.
2.3.1
Cache Line Replacement Policy
In general, the caches implement a least recently used (LRU) replacement policy. Each cache set maintains true LRU sta-
tus bits (MRU, nMRU and LRU) to determine which cache line is selected for replacement. However, software can influence
which cache line is replaced by marking memory pages as streaming, or by locking lines in the cache.
2.3.2
Cache Line Locking Support
The CACHE instruction is used to lock individual lines in the cache. A locked line is not subject to replacement. All four lines
in a set cannot be locked at once; at least one line is always available for replacement. To unlock individual cache lines use
ther discussion of the CACHE instruction.
2.3.3
Cache Streaming Support
Streaming is typically characterized as the processing of a large amount of transient instructions and/or data. In traditional
cache implementations (without explicit support for streaming), transient instructions and/or data quickly displace useful,
recently used items in the cache. This yields poor utilization of the cache and results in poor system performance.
The Au1 caches explicitly support streaming by placing instructions and/or data marked as streaming into way 0 of the
cache. This method ensures that streaming does not purge the cache(s) of useful, recently used items, while permitting
transient instructions and/or data to be cached. The CCA bits in the TLB entry indicate if a page contains streaming instruc-
tions and/or data. In addition, the PREF instruction is available to software to allow data to be placed in the data cache in
advance of its use.
2.3.4
Cache Line Allocation Behavior
When an instruction fetch misses in the instruction cache, or a data load misses in the data cache, a burst fill operation is
performed to fill the cache line from memory. The cache line is selected by the following algorithm:
MRU is most recently used
nMRU is next most recently used
nLRU is next least recently used
LRU is least recently used
Cache Miss:
if (Streaming CCA=6) then Replacement = 0,
else if (LRU is !Valid or !Locked) then Replacement = LRU
else if (nLRU is !Valid or !Locked) then Replacement = nLRU
else if (nMRU is !Valid or !Locked) then Replacement = nMRU
else Replacement = MRU
Cache Hit:
new MRU = Hit Way
Cache Line State
Bit 31 3029 2827 2625 24 2322 2120 1918 1716 1514131211 10
9
8
7
6
5
4
3
2
1
0
Physical Address Tag
D
S
L
V
Cache Address Decode
Bit 31 3029 2827 2625 24 2322 2120 1918 1716 1514131211 10
9
8
7
6
5
4
3
2
1
0
Virtual/Physical Address
Set Select
Byte Select