24
AMD Alchemy Au1550 Security Network Processor Data Book
Au1 Core and System Bus
30283D
2.3.8.1
Data Cache Initialization and Invalidation
Out of reset, all data cache lines are invalidated; thus the data cache is ready for use.
To invalidate the data cache in software, use a loop of CACHE indexed writeback invalidate instructions for each of the lines
in the cache:
li t0,(16*1024) # Cache size
li t1,32 # Line size
li t2,0x80000000 # First KSEG0 address
addu t3,t0,t2 # terminate address of loop
loop:
cache 1,0(t2) # Dcache indexed invalidate tag
addu t2,t1 # compute next address
bne t2,t3,loop
nop
2.3.8.2
Data Cache Line Fills
A data cache access is initiated in the execute stage which allows a cache hit or miss indication and all exceptions to be
signaled early in the cache stage. If the data address hits in the data cache, the data is available in the cache stage. If the
data address misses in the data cache and the address is cacheable, the data cache performs a burst fill to a cache line,
forwarding the critical word to the cache stage.
page 20. If the line selected contains modified data (cache line is valid and has its dirty bit set by a store hit), the cache line
is moved to a cast-out buffer, the cache line is filled from memory and the load request fulfilled, and then the cast-out buffer
is written to memory.
2.3.8.3
Data Cache Coherency
The data cache snoops coherent SBUS transactions to maintain data coherency with other SBUS masters (i.e., DMA). If a
coherent read transaction on the SBUS hits in the data cache, the data cache provides the data. If a coherent write transac-
tion on the SBUS hits in the data cache, the data cache updates its internal array with the data. If a coherent transaction
(read or write) misses in the data cache, the data cache array is unchanged by the transaction.
Loads and stores which hit in the data cache can bypass previous stores in cacheable regions. The read-allocate data
cache policy forwards store-misses to the write buffer. Subsequent loads and stores which hit in the data cache, and to a
different cache line address than store-misses, are fulfilled immediately (while store-misses may still be in the write buffer).
However, if a load address hits in a cache-line address of an item in the write buffer, the load is stalled until the write buffer
commits the corresponding store.
The data cache also maintains coherency with other caching masters. In the Au1550, the only caching master is the core.
When a load is serviced from another caching master, both caching masters set the shared bit for the affected cache line.
Then if a store occurs to a data cache line with the shared bit set, the cache line address is broadcast on the SBUS to inval-
idate cache lines in other caching masters that contain the same address.
The data cache is single-ported; therefore transactions on the SBUS are prioritized over accesses by the core. However,
the data cache design prevents the SBUS from saturating the data cache indefinitely, which ensures that the core can make
forward progress.
When changing the CCA encoding in Config0[K0] or the TLB to a different CCA encoding, software must ensure that data
integrity is not compromised by first pushing modified (dirty) data to memory within the page. This is especially important
when changing from a cacheable CCA encoding to a non-cacheable CCA encoding.
2.3.8.4
Data Cache Control
The cache-ability of data accesses is controlled by four mechanisms:
Config0[K0] field
The CCA bits in the TLB
The CACHE instruction
The PREF instruction
The Config0[K0] field contains a cache coherency attribute (CCA) setting to control the cache-ability of KSEG0 region. At
reset, this field defaults to 0b011, cacheable.