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AMD Alchemy Au1550 Security Network Processor Data Book
49
Au1 Core and System Bus
30283D
The Ethernet MAC DMA engine, for example, must read a packet from memory and generate a byte stream to the PHY for
transmission. For performance reasons, the MAC DMA engine reads the packet from memory (via the SBUS) 32-bits at a
time and so must manipulate the 4 bytes of each 32-bit SBUS data word to generate a byte stream.
Table 2-10 shows how
the byte stream is generated.
For peripheral DMA engines that access 8- or 16-bit FIFOs, the byte or halfword data is always placed on the SBUS in the
least-significant byte or halfword lane of the 32-bit SBUS data word. That is, the data is right-justified to start at bit 0. For
example, the 8-bit DMA channel for UART0 uses bits [7:0]. This behavior matches the register interface used by the Au1
2.9.2
Integrated Peripheral Bus
The integrated peripherals in the Au1550 expose programming registers to the Au1 core on the integrated peripheral bus.
The peripheral bus is an internal bus where peripherals that do not arbitrate for the SBUS (that is, do not perform DMA) are
located. All integrated peripheral registers are 32 bits wide, even though many bits in the registers may not be used.
Software must access all integrated peripheral registers as 32-bits; thus, software accesses to these registers are unaf-
fected by the endian mode of the Au1 core. (8- and 16-bit accesses to the peripheral bus are not supported.)
2.9.3
SBUS Masters
The SBUS supports multiple masters—the Au1 core and peripheral DMA engines. The SBUS arbitration scheme prevents
any master from consuming the entire SBUS bandwidth, while permitting low latency access to the SBUS for masters which
request the bus infrequently (such as peripherals).
The SBUS requestors in the Au1550 processor are as follows:
Slot 0: Au1 core (data cache, instruction cache, write buffer)
Slot 1: PCI controller
Slot 2: DDMA controller
Slot 3: Ethernet MAC controllers
Slot 4: Encryption engine
Slot 5: USB host controller
The Au1 presents a single request to the SBUS arbiter for the three possible requestors: the data cache, the instruction
cache and the write buffer. The data cache has the highest priority and the write buffer the lowest priority among the three
requests. However, the write buffer priority becomes the highest when the data cache requests a load to an address in the
write buffer to allow the write buffer to empty prior to fulfilling the data cache load.
Table 2-10. Peripheral Manipulation of SBUS Data for Endian Mode
Byte Stream
Little Endian
Big Endian
Byte 0
D of Word 0
A of Word 0
Byte 1
C of Word 0
B of Word 0
Byte 2
B of Word 0
C of Word 0
Byte 3
A of Word 0
D of Word 0
Byte 4
D of Word 1
A of Word 1
Byte 5
C of Word 1
B of Word 1
Byte 6
B of Word 1
C of Word 1
Byte 7
A of Word 1
D of Word 1
Byte 8
D of Word 2
A of Word 2
………