AMD Alchemy Au1550 Security Network Processor Data Book
251
AC97 Controller
30283D
8.4.2.3
AC97 Configuration
1)
Select the AC97 protocol (psc_sel[PS] = 0b100) and the clock source (psc_sel[CLK] = 0b10).
2)
Reset the codec. This enables the codec to drive bit clock, thus allowing the PSC configuration to continue. Reset is
performed as follows:
—Set psc_ac97rst[RST]. This holds ACRST# low. Clear psc_ac97rst[RST] after the minimum reset time required for
the external codec.
— Check for bit clock: Poll psc_ac97stat[CB] to see if this bit is set. Once set, configuration can continue.
3)
Enable the AC97 controller by writing to psc_ctrl[ENA]. This brings the configuration registers out of reset. Poll
psc_ac97stat[SR] to verify the PSC is out of reset.
4)
Configure for DMA or programmed I/O (psc_ac97cfg[DD]), FIFO sizes, and set psc_ac97cfg[DE] to enable the
device. Poll psc_ac97stat[DR] to determine if the device is ready.
The AC97 controller sends synchronization pulses during slot 0 and sets Tx slot valid bits in accordance with the AC97 pro-
tocol. All Tx and Rx data slots are cleared.
8.4.2.4
AC97 Power Management Considerations
The AC97 controller cannot be put into a low power state if the external codec is not in a power-down mode. The bit clock
provided by the external codec must be off.
All AC97 data transactions must have stopped and the Tx/Rx controllers disabled before writing to the codec power-down
register.
8.4.2.5
AC97 Transmit
The Tx and Rx controllers operate independently of each other. Each is enabled and disabled separately.
Before enabling the Tx controller, prepare the descriptors (if using DMA), or fill the Tx FIFO with data (if using programmed
I/O).
Software controls the number of Tx FIFO slots and the order in which the slots are filled within the FIFO.
psc_ac97cfg[TXSLOT] configures the number of enabled slots. Initialize Tx slots for programmed-I/O transfers before set-
ting psc_ac97pcr[TS] to prevent an underflow condition. This ensures that FIFO data for left and right channels remain
synchronized.
GPIO data is written separately using the GPIO output register psc_ac97gpo.
1)
Set the psc_ac97pcr[TS] start bit to begin transmitting data for the start of the next frame. Poll psc_ac97stat[TB] for
Tx controller ready.
2)
Tx data is popped from the FIFO by the external codec.
3)
Set the psc_ac97pcr[TP] stop bit to disable the Tx controller. Current frame is completed before controller is disabled.
Poll psc_ac97stat[TB] to verify that the Tx controller has been disabled.
4)
Set the psc_ac97pcr[TC] data clear bit to flush the Tx FIFO.
For underflow conditions, the Tx FIFO underflow event flag psc_ac97evnt[TU] is set. The corresponding interrupt can be
masked by setting psc_ac97msk[TU]. The PSC controller records at which slot the underflow occurred and begins trans-
mitting zeros and continues to the next frame up to the same underflow slot location.
Data is then checked in the Tx FIFO and for all frames at the same slot location. When data is available in the FIFO, the
controller begins transmitting data at the next frame at the same slot location where the underflow occurred. This sequence
prevents an out-of-sync condition with the Tx slot order.