AMD Alchemy Au1550 Security Network Processor Data Book
301
Ethernet MACs
30283D
17
IF
Inverse Filtering.
0
Normal operation.
1
Physical addresses are checked with inverse filtering. In other words
if the address passes a perfect address filter, the frame is not passed;
if the address fails a perfect filter, the frame is passed.
This is valid only during perfect filtering mode.
R/W
0
16
PB
Pass Bad Frames.
0
Normal operation.
1
All incoming frames that passed the address filtering are received
including runt frames, collided frames, or truncated frames caused by
buffer overflow.
The Packet Filter bit is set for error frames that pass the Address filtering.
Set Promiscuous Mode (bit 18) when all received bad frames are required.
R/W
0
15
HO
Hash Only Filtering Mode.
0
Perfect address filtering mode for physical addresses
1
Imperfect address filtering mode both for physical and multicast
addresses
Setting this bit is valid only if HP=1.
R/W
0
14
—
Reserved.
R
0
13
HP
Hash/Perfect Filtering Mode.
0
Address Check block does a perfect address filter of incoming frames
according the address specified in the MAC Address register.
1
Address Check block does imperfect address filtering of multicast
incoming frames according to the hash table specified in the multicast
Hash Table Register. If the Hash Only (HO) bit is set, then physical
addresses are imperfectly filtered too. If the Hash Only bit (HO) is
reset, then physical addresses are perfect address filtered according
to the MAC Address Register.
R/W
0
12
LC
Late Collision Control.
0
Abort frame transmission on a late collision.
1
Enable the retransmission of the collided frame even after the colli-
sion period (late collision).
In either case the Late Collision Status is appropriately updated in the
Transmit Packet Status.
This bit is valid only when operating in Half Duplex mode.
R/W
0
11
DB
Disable Broadcast Frames.
0
Forward all the broadcast frames to the application. (Packet Filter bit
is set.)
1
Disable the reception of broadcast frames. (Packet Filter bit is
cleared.)
R/W
0
10
DR
Disable Retry.
0
The MAC attempts 16 transmissions before signaling a retry error.
1
The MAC attempts transmission of a frame only once. When a colli-
sion is seen on the bus, the MAC ignores the current frame and goes
to the next frame and a retry error is reported in the Transmit Status.
This bit is valid only when operating in half duplex mode.
R/W
0
9
—
Reserved.
R
0
Bits
Name
Description
R/W
Default