110
AMD Alchemy Au1550 Security Network Processor Data Book
PCI 2.2 Bus Controller
30283D
4.1.1
Local PCI Configuration Register Block
Table 4-2 shows the register map for the Au1550 processor local configuration register block. The upper 256 bytes map to
the Au1550 PCI configuration header space defined by the PCI specification. The PCI controller can be configured to oper-
ate in Host or Satellite mode.
When the Au1550 processor is configured in Host mode, the PCI system configuration is done by the Au1550 processor. In
Host mode, the configuration registers and header space are only accessible internally. In Satellite mode, the PCI header
space is only accessible through PCI configuration cycles from an external host.
The Au1550 processor configuration registers must be written to the appropriate values before writing the header space
registers or configuring the system for either Host or Satellite mode. In Host mode, all configuration registers must be writ-
ten before accessing external devices.
4.1.1.1
PCI Cacheable Memory Region Register
The pci_cmem register configures the location of the cacheable memory window to PCI memory space. This feature
allows processor-initiated burst memory reads and writes to the PCI bus. Setting pci_cmem[E] enables the PCI cacheable
memory window. If the window is mapped to the first 512 Mbytes of the physical address space, the TLB is not needed; oth-
erwise, the TLB must be used to produce a physical address that hits in the pci_cmem address range with a CCA encod-
ing of 4. (Non-cacheable accesses are designated by the TLB producing the 36-bit physical address (0x4xxxxxxxx) with
CCA encoding of 2 or 7.)
A cacheable memory window size of 256 Kbytes to 2 Gbytes is supported. A PCI burst memory transaction is executed
when the following condition is met:
(physical_addr[31:18] & cm_mask) == cm_base
Table 4-2. PCI Bus Controller Configuration Registers
Offset from
0x0 1400 5000 (Physical)
Register Name
Description
0x0000
pci_cmem
PCI Cacheable Memory Region Register
0x0004
pci_config
Configuration/Error Register
0x0008
pci_b2bmaskcch
Back to Back Mask/Class Code High Register
0x000C
pci_b2bbase0venid
Back to Back Base 0/Vendor ID Register
0x0010
pci_b2bbase1subid
Back to Back Base 1/Subsystem ID Register
0x0014
pci_mwmaskdev
MBAR Address Mask/Device ID Register
0x0018
pci_mwbaserevccl
MBAR Window Base/Revision/Class Code Low Register
0x001C
pci_erraddr
PCI Error Address Register
0x0020
pci_specintack
PCI Special/Int Ack Cycle Register
0x0024
pci_prcfg
PCI Posted Read Configuration Register
0x0028
pci_praddr
PCI Posted Read Address Register
0x002C
pci_prstat
PCI Posted Read Status Register
0x0100
pci_id
Device and Vendor ID Register
0x0104
pci_statcmd
Status and Command Register
0x0108
pci_classrev
Class and Revision Code
0x010C
pci_param
Parameter Register (BIST, header type, latency timer, cache
line size)
0x0110
pci_mbar
Memory Base Address Register (MBAR)
0x0140
pci_timeout
Timeout Register