112
AMD Alchemy Au1550 Security Network Processor Data Book
PCI 2.2 Bus Controller
30283D
21
—
Reserved.
R
0
20
PD
PCI Disable. When this bit is set the PCI controller responds to target
accesses with a PCI RETRY.
R/W
1
19
BME
Byte mask enable for reads. This bit applies only to 8- and 16-bit read
accesses to memory and the configuration space. (The appropriate byte
lane masking is automatically applied for I/O reads less than 32 bits. Also,
writes of any length and destination always have appropriate byte lane
masking.)
0
Do not apply byte lane masking during 8-, 16-bit reads. (All byte
enables are asserted regardless of transaction size.)
1
Mask the appropriate byte lanes during 8-, 16-bit reads.
R/W
0
18
DR
Drive Mode.
0
33 MHz operation with less than 50 pF or 66 MHz operation with less
than 20 pF capacitive load.
1
33 MHz operation with more than 50 pF or 66 MHz operation with
more than 20 pF capacitive load.
R/W
0
17
—
Reserved.
R
0
16
NC
Target accesses to Au1550 memory are marked as non-coherent if this bit
is set.
R/W
0
15
IE
Interrupt Enable. This bit is reflected in bit 8 of offset 0x003C in configura-
tion space. If the Au1550 can generate a PCI interrupt in satellite mode,
this bit should be set.
R/W
0
14
—
Reserved.
R
0
13
IP
Enable the interrupt signal back to the interrupt controller if PCI_PERR# is
detected. This is pci_statcmd[31], the detected parity error bit.
R/W
0
12
IS
Enable the interrupt signal back to the interrupt controller if a PCI_SERR#
is generated. This is pci_statcmd[30], the signaled system error bit.
R/W
0
11
IMM
Enable the interrupt signal back to the interrupt controller if a Master-Abort
is asserted and the Au1550 processor is the master. This is
pci_statcmd[29], the received master abort bit.
R/W
0
10
ITM
Enable the interrupt signal back to the interrupt controller if a Target-Abort
is detected while the Au1550 processor is a Master. This is
pci_statcmd[28], the received target abort bit.
R/W
0
9
ITT
Enable the interrupt signal back to the interrupt controller if a Target-Abort
is asserted and the Au1550 is the Target. This is pci_statcmd[27], the sig-
naled target abort bit.
R/W
0
8
IPB
Enable the interrupt signal back to the interrupt controller if a PCI_PERR#
is detected, the Au1550 is the bus master and the perr_enable bit is set in
PCI configuration space. This is pci_statcmd[24], the master data parity
error bit.
R/W
0
7:6
SIC
These bits determine the address and data swapping of I/O and Configu-
ration cycles initiated by the Au1550 to/from external devices. See
Sectionbits.
R/W
0
5
ST
Swap data on PCI target transactions initiated by external PCI devices to/
from Au1550 memory.
R/W
0
4SM
Swap data on Au1550 processor initiated master memory transactions to/
from PCI.
R/W
0
3
AEN
When set this bit enables the Au1550 internal arbiter.
R/W
0
2
R2H
When set, PCI_REQ2# arbitrates into the high priority arbiter.
R/W
0
1
R1H
When set, PCI_REQ1# arbitrates into the high priority arbiter.
R/W
0
0CH
When set, the Au1550 processor arbitrates into the high priority arbiter.
R/W
0
Bits
Name
Description
R/W
Default