102
AMD Alchemy Au1550 Security Network Processor Data Book
Static Bus Controller
30283D
3.2.6.7
NAND Flash Programming Considerations
Booting from NAND Flash
NAND Flash boot code is restricted to the first page of the first block of the NAND Flash device. The boot code in this region
cannot loop or branch because the memory can only be read sequentially. The static memory controller increments the
address location for each column of the first page; however, during boot, the controller does not increment the page
address and recycle the column address back to 0x0.
The boot procedure is as follows:
1)
After reset, the NAND Flash controller’s bootload hardware issues the appropriate command and address cycles to
configure the NAND Flash device for reads.
2)
The controller issues a read command to the 0x0 block of the NAND Flash after power-up.
3)
All addresses to 0x1FC0xxxx are sent to the NAND Flash controller. Reads must be contiguous sequential words, up
to the page size of the device.
4)
Once the bootstrap code is fetched, system software must disable boot mode (mem_stndctrl[BOOT] = 0) and access
the device through software.
5)
Once the boot routine is transferred to the CPU core it starts execution of the boot routine.
Example Transactions for Typical NAND Flash Devices
Software controls the sequence for each transaction type using the NAND Flash device registers, and polling
mem_ststat[BSY] or waiting for the NAND-ready interrupt.
Reset Sequence:
1)
Write 0xFF to mem_stndcmd
2)
Poll mem_ststat[BSY], or wait for interrupt
Read Sequence:
1)
Write 0x00 to mem_stndcmd
2)
Write address byte to mem_stndaddr
3)
Write address byte to mem_stndaddr
4)
Write address byte to mem_stndaddr
5)
Write address byte to mem_stndaddr
6)
Poll mem_ststat[BSY], or wait for interrupt
7)
Read data from mem_stnddata up to page size (loop in 1-byte, 1 word, 8-word burst increments)
Write Sequence:
1)
Write 0x80 to mem_stndcmd
2)
Write address byte to mem_stndaddr
3)
Write address byte to mem_stndaddr
4)
Write address byte to mem_stndaddr
5)
Write address byte to mem_stndaddr
6)
Write data to mem_stnddata up to page size (loop in 1-byte, 1 word, 8-word burst increments)
7)
Write 0x10 to mem_stndcmd
8)
Poll mem_ststat[BSY], or wait for interrupt
9)
Read data from mem_stnddata for status