364
AMD Alchemy Au1550 Security Network Processor Data Book
Boot
30283D
11.3
Boot
For both hardware and runtime resets, the CPU boots from KSEG1 address 0xBFC00000 which is translated to physical
address 0x1FC00000; therefore, the system designer must place the start of the boot code at 0x1FC00000.
The BOOT signals determine where the processor boots from, as shown in
Table 11-1. The BOOT signal states can be
11.3.1
Endianness and 16-Bit Static Bus Boot
When booting from a 16-bit chip select on the static bus, the system designer must be sure the data format (endianness) is
consistent across the Au1 core, the static bus controller, and the software image itself. This section describes how to make
endianness consistent for both little- and big-endian systems.
NOTE: When programming ROM or Flash devices with a part programmer, take care to ensure that the programmer is not
swapping bytes or halfwords erroneously. The configuration of the part programmer is often a source of error when initially
bringing-up a new design.
11.3.1.1
16-Bit Boot for Little-Endian System
Booting from 16-bit ROM or Flash in a system that is intended to run the Au1 core in little-endian mode is straightforward.
For this example system, the boot code and/or the application is compiled for little-endian. Because the Au1 core defaults to
big-endian mode, the boot code must change the Au1 core endianness to little-endian before any data accesses (to the 16-
bit chip-select). The resulting boot code and/or application image is placed in the ROM/Flash memory in the little-endian
format.
Even though the Au1 core starts in big-endian mode, the static bus controller properly retrieves instructions needed to boot
the system since the application image is in little-endian format and the static bus controller defaults to little-endian ordering
out of reset.
Table 11-1. Boot Device Selection (BOOT[2:0])
BOOT[2:0]
Boot Device
0
32-bit ROM on RCS0# of the static bus controller.
1
16-bit ROM on RCS0# of the static bus controller.
2, 3
Reserved.
4
PCI on the PCI controller.
5
Reserved.
6
16-bit NAND on RCS0# of the static bus controller.
7
8-bit NAND on RCS0# of the static bus controller.