318
AMD Alchemy Au1550 Security Network Processor Data Book
Ethernet MACs
30283D
9.4.5.1
Media Independent Interface (MII)
Each MAC provides a media independent interface (MII) to connect to a PHY device.
Figure 9-3 shows the MAC0 MII sig-
nals connected to a PHY device. (MAC1 has an identical interface with signal names beginning with N1.)
Note that unused MII signals can be left unconnected except for those MII signals multiplexed with a GPIO signal function.
The N1TXEN and N1TXD[3:0] signals on MAC1 are multiplexed with GPIO[24] and GPIO[28:25] respectively and need to
be pulled up.
Figure 9-3. Connecting MAC0 to a PHY Device through MII
N1RXDV
I
Indicates that a receive frame is in process and that the data on N1RXD[3:0] is valid.
N1RXD[3:0]
I
RXD[3:0] is a 4-bit wide data bus driven by the PHY to the MAC synchronous with
N1RXCLK. For each N1RXCLK period in which N1RXDV is asserted, RXD[3:0] transfers
four bits of recovered data from the PHY to the MAC. While N1RXDV is negated, RXD[3:0]
has no effect on the MAC.
N1CRS
I
The PHY asserts N1CRS when either transmit or receive medium is non idle. The PHY
negates N1CRS when both the transmit and receive medium are idle. N1CRS is an asyn-
chronous input.
N1COL
I
The PHY asserts N1COL upon detection of a collision on the medium and continues to
assert N1COL while the collision condition persists. N1COL is an asynchronous input.
The N1COL signal is ignored by the MAC when operating in full duplex mode.
N1MDC
O
N1MDC is sourced by the MAC to the PHY as the timing reference for transfer of informa-
tion on the N1MDIO signal. N1MDC is an aperiodic signal that has no maximum high or
low times. The N1MDC frequency is fixed at SBUS clock divided by 160.
N1MDIO
IO
N1MDIO is the bidirectional data signal between the MAC and the PHY that is clocked by
N1MDC.
Requires an external 1.5 kohm pull-up resistor.
Table 9-21. Ethernet Signals (Continued)
Signal
Input/
Output
Description
N0TXCLK
N0TXEN
N0TXD[3:0]
N0RXCLK
N0RXDV
N0RXD[3:0]
N0CRS
N0COL
N0MDC
N0MDIO
MAC0
Transmit Clock
Transmit Enable
Transmit Data [3:0]
Receive Clock
Receive Data Valid
Receive Data [3:0]
Carrier Sense Output
Collision Detect
Management Data Clock
Management Data I/O
Au1550 Processor
10/100M
PHY
Media-Independent
Interface
PHY Layer
Device
TXCLK
TXEN
TXD[3:0]
RXCLK
RXDV
RXD[3:0]
CRS
COL
MDC
MDIO
+3.3 V