AMD Alchemy Au1550 Security Network Processor Data Book
85
Static Bus Controller
30283D
3.2.1.3
Static Chip Select Address Configuration Registers (mem_staddrn)
The static memory chip select address configuration registers (mem_staddrn) assign an address range for each chip
select. As shown below, each register contains a base address, an address comparison mask, and an enable bit.
Once enabled, a chip select is asserted when the following condition is met:
(sysbus_addr & cs_mask) == cs_base
where:
sysbus_addr: 36-bit physical address output on the internal SBUS (from the TLB for memory-mapped regions)
cs_mask: address comparison mask taken from CSMASK
cs_base: chip select base address taken from CSBA
Chip select regions must be programmed so that each chip select occupies a unique area of the physical address space.
Programming overlapping chip select regions results in undefined operation.
mem_staddr0
Offset = 0x1008
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
E
CSBA
CSMASK
Def. 000
Rs
0001111111000011111111111111
mem_staddr1
mem_staddr2
mem_staddr3
Offset = 0x1018
Offset = 0x1028
Offset = 0x1038
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
E
CSBA
CSMASK
Def. 00001111111111111111111111111111
Bits
Name
Description
R/W
Default
31:29
—
Reserved.
R
0
28
E
Enable.
0
Disable the chip select.
1
Enable the chip select.
R/W
0, except for
mem_staddr0
(Note 1)
Note 1.
The enable (E) bits for chip selects RCS1#, RCS2#, and RCS3# are automatically cleared (disabled) coming out of a runtime or
hardware reset. For RCS0#, however, the reset value of the E bit depends on BOOT[2:0]. If the BOOT[2:0] signals indicate that
a memory device on the static bus is used for the boot vector, RCS0# is enabled (mem_staddr0[E] = 1); otherwise, RCS0# is
27:14
CSBA
Chip select base address cs_base[31:18].
cs_base is the physical base address for the chip select.
cs_base[35:32] is determined by mem_stcfgn[DTY].
cs_base[31:18] = CSBA.
cs_base[17:0] = 0.
R/W
0x3FFF, except for
mem_staddr0 where
the default value is
0x7F0.
13:0
CSMASK
Chip select address mask cs_mask[31:18].
cs_mask is used to decode the chip select.
cs_mask[35:32] = 0xF.
cs_mask[31:18] = CSMASK.
cs_mask[17:0] = 0.
R/W
0x3FFF