AMD Alchemy Au1550 Security Network Processor Data Book
337
Clocks
30283D
10.1.3
PLL Control Registers
The two independent PLLs in the Au1550 processor drive the CPU clock and the auxiliary clock. Each PLL has its own con-
trol register. When programming the PLL control registers, the system designer must not violate the rated frequency limits
of the Au1550 processor; configuring the PLLs outside this frequency range causes undefined behavior.
The system must provide the correct voltage for the operating frequency before changing the CPU clock. See
Section 14.310.1.3.1
CPU PLL Control
The CPU PLL control register (sys_cpupll) resets to its default value only for a hardware reset. That is, after Sleep, and
during a runtime reset the CPU PLL retains its frequency. This register is read/write; however, a read from this register is
valid only after it has been initialized with a write.
The CPU PLL register should be modified only when all integrated peripherals and the SDRAM controller are disabled.
After writing to the sys_cpupll register, bus clocks shut off and approximately 40 s elapse while the CPU PLL locks to the
new frequency. During this period instructions are not executed and interrupts are not serviced. Interrupts are serviced
once execution begins again at the new frequency.
Table 10-4 shows the rated CPU frequency alongside the actual CPU frequency and PLL multiplier when using a 12 MHz
crystal.
sys_cpupll
Offset = 0x0060
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
PLL[5:0]
Def. 00000000000000000000000000010000
Bits
Name
Description
R/W
Default
31:6
—
Reserved.
R/W
0
5:0
PLL
CPU PLL Multiplier. Determines the integer multiplier used to multiply the
CPU PLL to generate the CPU clock.
For example, with the default of 16 and a 12 MHz OSC frequency, the CPU
clock frequency is 192 MHz.
PLL multiplier values that place the clock frequency outside of rated limits
are invalid.
0–15:
Reserved and undefined
16–(n-1): Valid PLL multiplier
n–63:
Reserved and undefined
n is the smallest PLL multiplier that would cause the CPU clock frequency
R/W
0x10
Table 10-4. Rated and Actual CPU Frequencies Using a 12 MHz Crystal
Rated Frequency (MHz)
Actual Frequency (MHz)
CPU PLL Multiplier
500
492
41
400
396
33
333
336
28