AMD Alchemy Au1550 Security Network Processor Data Book
61
DDR/SDR SDRAM Memory Controller
30283D
3.1.2.4
Precharge All Command Register
Writing any value to the mem_sdprecmd register issues a precharge all command to all enabled chip selects. This can be
used for initialization sequences that require certain operations to be performed in a deterministic order.
3.1.2.5
Auto Refresh Command Register
Writing to the mem_sdautoref register performs an AUTO REFRESH command on all enabled chip selects. This can be used
for initialization sequences that require specific operations to be performed in a deterministic order. See also
SectionReading from the mem_sdautoref register returns the current value of the refresh timer.
3.1.2.6
Self Refresh Toggle Command Register
Writing to this register toggles the self refresh mode. Enter self refresh mode as follows:
1)
The first write (and subsequent odd-numbered writes) to mem_sdsref causes the controller to issue a SELF REFRESH
command to all enabled chip selects.
2)
System software can then poll the self-refresh flag (mem_sdstat[SLF]) to confirm the command has completed.
3)
When mem_sdstat[SLF]=1, the memory controller negates the clock-enable signal DCKE, and software can safely
disable memory clocks by clearing mem_sdconfiga[CE].
Exit self refresh mode as follows:
1)
System software must first enable memory clock(s) in mem_sdconfiga[CE].
2)
A second write (and subsequent even-numbered writes) to mem_sdsref causes the memory controller to clear
mem_sdstat[SLF] and assert the clock-enable signal DCKE.
3)
On the assertion of DCKE, the memory controller waits ((mem_sdconfigb[TXSR]+1) * 16) clocks before issuing a
new command.
System Note: VDDI powers the SDRAM controller. If VDDI is disabled as part of a Sleep or Hibernate sequence and the
SDRAM controller is in self-refresh mode, the SDRAM controller state machine exits self-refresh mode, even though the
DCKE signal remains negated and the actual SDRAM memory continues to refresh itself. When VDDI is re-enabled, the first
write to mem_sdsref causes the SDRAM controller state machine to re-enter self-refresh mode. (The DCKE signal
mem_sdprecmd
Offset = 0x008C0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
PA
Def. XXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXX
Bits
Name
Description
R/W
Default
31:0
PA
Writing to PA causes a precharge command to be issued to all enabled
chip selects.
W
UNPRED
mem_sdautoref
Offset = 0x08C8
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
AR
Def. XXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXX
Bits
Name
Description
R/W
Default
31:0
AR
Writing a 0 to AR causes an AUTO REFRESH command to be issued to all
enabled chip selects.
R/W
UNPRED