316
AMD Alchemy Au1550 Security Network Processor Data Book
Ethernet MACs
30283D
Transmit Buffer Address/Enable Register
This register contains the starting address for the transmit memory buffer. The MAC DMA transfers the number of bytes
designated in the Length register.
The buffer for the DMA must be cache line aligned so the lowest 5 bits are not used as part of the address. These bits have
been employed as done and enable bits and are exclusive of the address.
Transmit Buffer Length Register
This register contains the length of the memory buffer in bytes to be transmitted.
macdmam_txnaddr
Offset = 0x0004
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
ADDR[31:5]
CB
DN EN
Def. 0000000000000000000000000000
X
0
Bits
Name
Description
R/W
Default
31:5
ADDR
Buffer Address. Upper 27 bits of the starting physical address for the DMA
buffer—but not including address bits [35:32]. This address must be cache
line (32 bytes) aligned so only 27 bits are used.
This address must be written for each DMA transfer because the address
does not remain after the transaction is enabled.
R/W
0
4
—
Reserved.
R
0
3:2
CB
Current Buffer. Current DMA transmit buffer.
R
UNPRED
1
DN
Transaction Done. This bit is set by hardware to indicate that the transmit
transaction has been completed and that the transmit packet status is
valid.
Done bits for all TX and RX buffers are or’ed together for this interrupt so a
high level interrupt is used.
This bit must be cleared explicitly by software after checking for done. This
also clears the interrupt.
R/W
UNPRED
0
EN
MAC DMA Enable. When set, this bit enables a DMA transmit transaction
from the memory location designated in ADDR.
R/W
macdmam_txnlen
Offset = 0x0008
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
LEN[13:0]
Def. 00000000000000000000000000000000
Bits
Name
Description
R/W
Default
31:14
—
Reserved.
R
0
13:0
LEN
Buffer Length. Specifies the length of the memory buffer (in bytes).
When the normal bit is set, the length can only be up to 0x0800 bytes.
When the jumbo packets are enabled in the enable register, the length can
be set up to 0x2800 bytes.
R/W
0