AMD Alchemy Au1550 Security Network Processor Data Book
103
Static Bus Controller
30283D
Block Erase Sequence:
1)
Write 0x60 to mem_stndcmd
2)
Write address byte to mem_stndaddr
3)
Write address byte to mem_stndaddr
4)
Write address byte to mem_stndaddr
5)
Write 0xD0 to mem_stndcmd
6)
Poll mem_ststat[BSY], or wait for interrupt
7)
Write 0x70 to mem_stndcmd
8)
Read data from mem_stnddata for status
3.2.7
Static Bus Controller Programming Considerations
3.2.7.1
Modifying the RCS0# Boot Configuration
When booting from the static memory controller, the default timing mode for RCS0# is synchronous mode
(mem_stcfg0[S]=1). If the system requires the timing mode be changed to asynchronous mode, mem_sttime0 must be
updated before mem_stcfg0 as follows:
1)
Modify the timing parameters as needed in mem_sttime0.
2)
Modify mem_stcfg0.
3)
Issue a SYNC instruction.
If mem_stcfg0 is updated first, the chip select timing may be invalid for the Flash/ROM boot devices during the time
between the updates to mem_stcfg0 and mem_sttime0. A processor instruction fetch during this period would return
invalid data.
3.2.7.2
Chip Select Clocking
All chip selects share a common clock derived from the SBUS clock. When a chip select is configured for synchronous
mode (mem_stcfgn[S] = 1), the static bus controller provides the clock externally on RCLK. Once a chip select is config-
ured for synchronous operation, the RCLK output begins running and continues to run even when the chip select is not
For interface timing, each chip select has a static timing register mem_sttimen to adjust the access timing parameters for
PWAIT# for PCMCIA devices) is provided to delay each access, if needed.
3.2.7.3
Page Mode Transfers
The static bus controller provides a page mode for quick read access to sequential locations in memory. Setting
mem_stcfgn[PM] selects page mode operation for the chip select. The burst size (4 or 8 beats) for page mode transfers is
programmed in mem_stcfgn[BS].
Depending on the speed of the external memory device, the system designer can adjust two timing parameters in
mem_sttimen for page mode transfers:
Ta is the time from chip select assertion to the first beat of valid data. Ta is the time required for the initial access to a
peripheral device. Ta must allow time for the peripheral device to load its read buffer or activate the next page. Note that
the page size depends on the peripheral device.
Tpm is the time between beats.
The static bus controller does not check for page boundaries during page mode reads. The addressing is sequential
regardless of alignment. An access which crosses a page boundary may return invalid data if Tpm does not allow enough
time for the external memory device to update its read buffer or activate the next page. If the system designer cannot
ensure adequate address alignment to avoid crossing page boundaries, Tpm must be long enough to accommodate poten-
tial page updates.