AMD Alchemy Au1550 Security Network Processor Data Book
397
Signal Descriptions
30283D
GPIO[10]
IOZ
General Purpose I/O. Muxed with U3DSR#. GPIO[10]
is the default signal coming out of hardware reset,
runtime reset, and Sleep.
Note:
For systems that use the UART3 interface
without the optional modem control signals
(sys_pinfunc[UR3]=0), the modem status
interrupts
must
be
disabled
(uart3_inten[MIE]=0) to avoid false UART3
interrupts when using GPIO[9], GPIO[10],
GPIO[11], or GPIO[12] as an input.
HIZ
LV
GPIO[11]
IOZ
General Purpose I/O. Muxed with U3DCD#. GPIO[11]
is the default signal coming out of hardware reset,
runtime reset, and Sleep.
Note:
For systems that use the UART3 interface
without the optional modem control signals
(sys_pinfunc[UR3]=0), the modem status
interrupts
must
be
disabled
(uart3_inten[MIE]=0) to avoid false UART3
interrupts when using GPIO[9], GPIO[10],
GPIO[11], or GPIO[12] as an input.
HIZ
LV
GPIO[12]
IOZ
General Purpose I/O. Muxed with U3RI#. GPIO[12] is
the default signal coming out of hardware reset, runt-
ime reset, and Sleep.
Note:
For systems that use the UART3 interface
without the optional modem control signals
(sys_pinfunc[UR3]=0), the modem status
interrupts
must
be
disabled
(uart3_inten[MIE]=0) to avoid false UART3
interrupts when using GPIO[9], GPIO[10],
GPIO[11], or GPIO[12] as an input.
HIZ
LV
GPIO[13]
IOZ
General Purpose I/O. Muxed with U3RTS#. GPIO[13]
is the default signal coming out of hardware reset,
runtime reset, and Sleep.
HIZ
LV
GPIO[14]
IOZ
General Purpose I/O. Muxed with U3DTR#. GPIO[14]
is the default signal coming out of hardware reset,
runtime reset, and Sleep.
HIZ
LV
GPIO[15]
IOZ
General Purpose I/O.
HIZ
LV
GPIO[16]
IOZ
General Purpose I/O. Muxed with PSC0_SYNC1.
PSC0_SYNC1 is the default signal coming out of
hardware reset, runtime reset, and Sleep.
Note:
The GPIO[16]/PSC0_SYNC1 pin is driven
high coming out of reset.
NA
LV
GPIO[17]
IOZ
General Purpose I/O. Muxed with PSC1_SYNC1.
PSC1_SYNC1 is the default signal coming out of
hardware reset, runtime reset, and Sleep.
Note:
The GPIO[17]/PSC1_SYNC1 pin is driven
high coming out of reset.
NA
LV
Table 13-3. External Signals (Continued)
Signal
Type
Description
Reset
During
Sleep
HW
Run
Time