374
AMD Alchemy Au1550 Security Network Processor Data Book
EJTAG Implementation
30283D
12.4.1.5
Processor Data Mask/Upper Overlay Address Mask
This register is dual purpose depending on the value of the Overlay Enable bit in the Bus Break Control and Address Mask
(ejtag_pbcam[OE]).
This register specifies the mask value for the Processor Data Mask register. Each bit corresponds to a bit in the data regis-
ter.
12.4.1.6
Processor Bus Break Control and Address Mask
This register selects the processor bus match function to enable debug break or trace trigger. It also includes control bits to
enable comparison as well as mask bits to exclude address bits from comparison. All processor break exceptions are
imprecise.
ejtag_pdm (ejtag_pbcam[OE] = 0)
Offset = 0x0308
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
PDM
Def. xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Bits
Name
Description
R/W
Default
31:0
PDM[31:0]
Processor data mask
0
Data bit is not masked, data bit is compared.
1
Data bit is masked, data bit is not compared.
R/W
UNPRED
ejtag_pdm (ejtag_pbcam[OE] = 1)
Offset = 0x0308
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
UOAM
Def. xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Bits
Name
Description
R/W
Default
31:24
UOAM
Upper Overlay Address Mask. These bits represent bits [31:24] of the
address mask and are combined with the LAM and HAM fields to create a
complete 36 bit address mask.
0
Address bit is not masked, address bit is compared.
1
Address bit is masked, address bit is not compared.
R/W
UNPRED
23:0
—
Reserved.
—
ejtag_pbcam
Offset = 0x030C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
LAM
DC DU
DIU
OE
BE
Def. xxxxxxxxxxxxxxxxxxxxxxxxxxxx
0000
Bits
Name
Description
R/W
Default
31:8
LAM
Address Mask. These bits specify the mask value for the lower 24 bits of
the processor address register (ejtag_pab[23:0]). Each bit corresponds to
the same bit in ejtag_pab.
0
Address bit is not masked, address bit is compared.
1
Address bit is masked, address bit is not compared.
R/W
UNPRED
7
DC
Data Store to Cached Area. This bit enables the comparison on processor
address and data bus for data store to the cached area.
0
Processor address and data is not compared for storing data to the
cached area.
1
Processor address and data is compared for storing data to the
cached area.
R/W
UNPRED