AMD Alchemy Au1550 Security Network Processor Data Book
241
AC97 Controller
30283D
8.4.1.1
AC97 Configuration Register
The AC97 configuration register (psc_ac97cfg) configures the operational parameters for the AC97 protocol. While the
device enable bit is set, do not modify any fields other than psc_ac97cfg[DE].
psc_ac97cfg
Offset = 0x0008
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
RT
TT
DD DE SE
LEN
TXSLOT
RXSLOT
GE
Def. 00000000000000000000000000000000
Bits
Name
Description
R/W
Default
31:30
RT
Rx FIFO Threshold.
00
1 data entry
01
2 data entries
10
4 data entries
11
8 data entries
For DMA transfers (psc_ac97cfg[DD]=0), the threshold must match the
source transfer size (STS) programmed in the descriptor.
For programmed I/O (psc_ac97cfg[DD]=1), once the number of data
entries rises to the threshold, a receive request (RR) is triggered in the
event and status registers.
R/W
0
29:28
TT
Tx FIFO Threshold.
00
1 empty slot
01
2 empty slots
10
4 empty slots
11
8 empty slots
For DMA transfers (psc_ac97cfg[DD]=0), the threshold must match the
destination transfer size (DTS) programmed in the descriptor.
For programmed I/O (psc_ac97cfg[DD]=1), once the number of empty
FIFO slots matches the threshold, a transmit request (TR) is triggered in
the event and status registers.
R/W
0
27
DD
Disable DMA Transfers.
0
Enable DMA transfers. Software prepares buffers and descriptors,
and the DDMA controller handles the transfers.
1
Programmed I/O. Software handles each transfer directly by using
the data register and monitoring the FIFO events.
R/W
0
26
DE
Device Enable.
0
Disable the AC97 controller.
1
Enable the AC97 controller.
Do not modify any other fields in psc_ac97cfg while the AC97 controller is
enabled (psc_ac97stat[DR] = 1).
R/W
0
25
SE
Secondary Codec Enable.
0
Disable secondary codec support.
1
Enable secondary codec support. The AC97 controller transmits all
valid Tx slots (based on Tx-slot-valid configuration bits) on each
requested frame. A frame request is detected each time the primary
codec requests one (or more) Tx slots. The primary and secondary
codecs must sample at the same variable rate.
R/W
0
24:21
LEN
Data Length. Must be between 8 and 20 bits. This value is used to deter-
mine the MSb of Tx and Rx data.
Data length = (LEN * 2) + 2
Be sure to program the data length between 8-20 (LEN between 3-9) for
proper AC97 operation.
R/W
0