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AMD Alchemy Au1550 Security Network Processor Data Book
Power Management
30283D
10.4.1.1
Returning from Idle
The processor wakes from the idle state (IDLE0 or IDLE1) upon receiving an interrupt. The time required for the processor
core to return to normal execution is as follows:
Five to ten CPU clocks are needed to restart clocks to the CPU.
It takes an additional ten CPU clocks for the core to recognize the interrupt and begin fetching the interrupt service
routine.
Therefore, a maximum of 20 CPU clocks are required to resume normal instruction pipeline execution. If the interrupt ser-
vice routine is in the instruction cache, the instruction returns immediately; otherwise, there is an additional delay while
fetching the instruction from memory.
10.4.2
Peripheral Power Management
Peripheral power management is handled through clock management and disabling of unused peripherals.
Table 10-8 lists
the peripherals and their related power management registers. The actual register descriptions should be referred to for
programming details.
When separate reset/peripheral enable and clock-enable bits are provided, the reset must be applied first, and then the
clocks should be disabled. This simplifies programming, as the suggested bring up sequence is typically to first enable
clocks and then subsequently to bring the peripheral out of reset.
Table 10-8. Peripheral Power Management
Peripheral
Power
Management
Register
Power Management Strategy
USB Host
usbh_enable
When the USB host is not in use the E bit can be cleared to disable
the host. The CE bit should also be cleared to disable clocks to the
block.
USB Device
usbd_enable
When the USB device is not in use the E bit can be cleared to dis-
able the host. The CE bit should also be cleared to disable clocks to
the block.
Ethernet MACn
macen_macn
When either block is not being used, the respective E[2:0] bits should
be cleared to disable the MAC, and the CE bit should be cleared to
gate clocks to the MAC.
UARTn
uartn_enable
When a UART is not being used, the E bit should be cleared to hold
the part in reset and the CE bit should be cleared to disable clocks to
the block.
Primary General
Purpose I/O (GPIO)
Controller
sys_trioutclr
Although there is not a specific low-power configuration for the pri-
mary GPIOs, tristating the unused GPIOs minimizes their power
usage.
Secondary General
Purpose I/O (GPIO2)
Controller
gpio2_enable
If no GPIO2 signals are being used, the GPIO2 module reset (MR)
bit should be set to place the module in reset. Also, clear the CE bit
to disable clocks to the block. (By default, the GPIO2 module is dis-
abled coming out of reset.)
TOY and RTC
sys_cntrctrl
If both the TOY and RTC are not being used, then disable the oscilla-
tor.
PSC
pscn_ctrl
If a PSC is not in use, clear the ENA bit to disable the block.