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AMD Alchemy Au1550 Security Network Processor Data Book
Primary General Purpose I/O and Pin Functionality
30283D
10.3
Primary General Purpose I/O and Pin Functionality
The Au1550 processor contains two separate GPIO blocks (primary and secondary). This section covers the programming
model for the primary general purpose I/O (GPIO) signals. The Au1550 processor supports 43 GPIOs, 27 of which are con-
trolled by the primary GPIO block. For a description of the programming model for the secondary GPIO block see
SectionThis section also documents how to change the functionality of multiplexed pins. These pins can function at the system
level as a GPIO signal, or they can be assigned a signal function dedicated to an integrated peripheral device.
Each GPIO can be configured as either an input or an output. The GPIO ports also can be connected to the internal inter-
tion on interrupts.
10.3.1
Pin Functionality
To maximize the functionality of the Au1550 processor, many of the pins have multiple uses. If a pin is programmed for a
certain use, any other functionality associated with that pin cannot be utilized at the same time. In other words, a pin cannot
be used as a GPIO at the same time it is assigned to a peripheral device.
For example, if sys_pinfunc[U3T] is cleared configuring the pin as U3TXD, GPIO[23] cannot be used as a GPIO nor can
the GPIO be configured as an interrupt. Conversely if sys_pinfunc[U3T] is set configuring the pin as GPIO[23], U3TXD
(and thus the UART3 interface) is not usable. GPIO[23] can be used as a GPIO and to generate interrupts. GPIO[23] can
also be used as a clock source for frequency generator 3 (FREQ3).
multiplexed on one pin show the shared function in parentheses.)
10.3.1.1
Pin Function
This register resets to its default state at hardware reset, runtime reset and Sleep.
sys_pinfunc
Offset = 0x002C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
PSC3
PSC2
CS USB U3T U1R U1T
EX1 EX0
U3
MBSa
NI2 U0 MBSb S1 S0
Def. 00000000011111100111000000111111
Bits
Name
Description
R/W
Default
31:23
—
Reserved
—
22:20
PSC3
GPIO[215:211]/PSC3.
000 Pins are configured as PSC3_CLK, PSC3_D0, PSC3_D1,
PSC3_SYNC0, PSC3_SYNC1. Use for AC’97 or SPI.
001 Pins are configured as PSC3_CLK, PSC3_D0, PSC3_D1,
PSC3_SYNC0, GPIO[211]. Use for I2S.
011 Pins are configured as PSC3_CLK, PSC3_D0, GPIO[213:211]. Use
for SM bus.
111 Pins are configured as GPIO[215:211].
All other values are reserved.
R/W
0x7
19:17
PSC2
GPIO[210:206]/PSC2.
000 Pins are configured as PSC2_CLK, PSC2_D0, PSC2_D1,
PSC2_SYNC0, PSC2_SYNC1. Use for AC’97 or SPI.
001 Pins are configured as PSC2_CLK, PSC2_D0, PSC2_D1,
PSC2_SYNC0, GPIO[206]. Use for I2S.
011 Pins are configured as PSC2_CLK, PSC2_D0, GPIO[208:206]. Use
for SM bus.
111 Pins are configured as GPIO[210:206].
All other values are reserved.
System Note: When sys_pinfunc[19] = 1, GPIO[23] is available as an
optional clock source for frequency generator 3 (FREQ3); see
SectionR/W
0x7