AMD Alchemy Au1550 Security Network Processor Data Book
229
Inter-IC Sound Controller (I2S)
30283D
8.3.1.1
I2S Configuration Register
The I2S configuration register (psc_i2scfg) configures the operational parameters for the I2S protocol. While the device
enable bit is set, do not modify any fields other than psc_i2scfg[DE].
psc_i2scfg
Offset = 0x0008
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
RT
TT
DD DE
WS
WI
DIV
BI BUF LSJ XM
LEN
LB
MLF MS
Def. 00000000000000000000000000000000
Bits
Name
Description
R/W
Default
31:30
RT
Rx FIFO Threshold.
00
1 data entry
01
2 data entries
10
4 data entries
11
8 data entries
For DMA transfers (psc_i2scfg[DD]=0), the threshold must match the
source transfer size (STS) programmed in the descriptor.
For programmed I/O (psc_i2scfg[DD]=1), once the number of data entries
rises to the threshold, a receive request (RR) is triggered in the event and
status registers.
R/W
0
29:28
TT
Tx FIFO Threshold.
00
1 empty slot
01
2 empty slots
10
4 empty slots
11
8 empty slots
For DMA transfers (psc_i2scfg[DD]=0), the threshold must match the des-
tination transfer size (DTS) programmed in the descriptor.
For programmed I/O (psc_i2scfg[DD]=1), once the number of empty FIFO
slots matches the threshold, a transmit request (TR) is triggered in the
event and status registers.
R/W
0
27
DD
Disable DMA Transfers.
0
Enable DMA transfers. Software prepares buffers and descriptors,
and the DDMA controller handles the transfers.
1
Programmed I/O. Software handles each transfer directly by using
the data register and monitoring the FIFO events.
R/W
0
26
DE
Device Enable.
0
Disable the I2S controller.
1
Enable the I2S controller.
Do not modify any other fields in psc_i2scfg while the I2S controller is
enabled (psc_i2sstat[DR] = 1).
R/W
0
25:22
-
Reserved
-0
21:16
WS
Word strobe. Applies to master mode only. Programs the number of
I2SCLK cycles for left or right channel data.
Word strobe = 2 * (WS + 1) * I2SCLK cycles
For example, to configure 128Fs, let WS=63.
R/W
0
15
WI
Word Strobe Invert. Selects the I2SWORD polarity.
0
I2SWORD is active-high for the first channel.
1
I2SWORD is active-low for the first channel.
R/W
0
14:13
DIV
00
I2SCLK = I2SMCLK / 2
01
I2SCLK = I2SMCLK / 4
10
I2SCLK = I2SMCLK / 8
11
I2SCLK = I2SMCLK / 16
R/W
0