AMD Alchemy Au1550 Security Network Processor Data Book
355
Power Management
30283D
Not Using Hibernate (FWTOY# = VDDX)
A system that does not use Hibernate should tie FWTOY# to VDDX, so that FWTOY# remains negated when VDDXOK
rises.
10.4.4.6
Software Visibility
Software visible differences due to Hibernate are as follows:
The oscillator enable sys_cntrctrl[EO] is not reset on VDDXOK rise if due to a Hibernate wakeup.
Software can set sys_wakemsk[D2] (Hibernate match enable) to trigger the assertion of WAKE# when the TOY timer
equals sys_toymatch2.
Hardware sets sys_wakesrc[DW] (Hibernate wakeup) if FWTOY# is asserted at the time of VDDXOK rise.
Additionally, hardware sets sys_wakesrc[M2D] (Hibernate time match) if a Hibernate wakeup is accompanied by a
WAKE# assertion due to a TOY timer match in sys_toymatch2. Software must clear sys_wakesrc[M2D] (any write).
Regardless of Hibernate wakeup, the initial power-up bit sys_wakesrc[IP] is set on VDDXOK rise.
10.4.5
Power Management Registers
The power management registers and their associated offsets are listed in
Table 10-10. These registers are located off of
10.4.5.1
Scratch Registers
The scratch registers keep their values through Sleep, Hibernate, and runtime resets. These registers allow the system pro-
grammer to save user-defined state information or a pointer to a context so that the previous context can be restored when
coming out of Sleep, if needed. The scratch registers have unpredictable default values after a hardware reset.
Table 10-10. Power Management Registers
Offset (Note 1)
Register Name
Description
Reset Type
0x0018
sys_scratch0
User-defined register that retains its value through
Sleep.
Hardware
0x001C
sys_scratch1
User-defined register that retains its value through
Sleep.
Hardware
0x0034
sys_wakemsk
Sets which GPIO or whether TOY match can cause
Sleep wakeup
Hardware
0x0038
sys_endian
Sets Big or Little Endian
Hardware & Runtime
0x003C
sys_powerctrl
Sets SBUS divider and power-up time
Mixed (see register
description)
0x005C
sys_wakesrc
Gives source of Sleep wakeup
Hardware
0x0078
sys_slppwr
Initiates power state for Sleep mode
Hardware
0x007C
sys_sleep
Initiates Sleep mode
Hardware
sys_scratch0
Offset = 0x0018
sys_scratch1
Offset = 0x001C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
SCRATCH[31:0]
Def. XXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXX
Bits
Name
Description
R/W
Default
31:0
SCRATCH
User-defined information.
R/W
UNPRED