86
AMD Alchemy Au1550 Security Network Processor Data Book
Static Bus Controller
30283D
3.2.1.4
NAND Control Register
The NAND Flash control register enables booting and interrupts from NAND Flash. This register is write-only.
3.2.1.5
Static Bus Status Register (mem_ststat)
The static bus status register (mem_ststat) reflects the state of the flow-control signals associated with the static bus:
PWAIT#, EWAIT#, and RNB. Software drivers can poll mem_ststat for device status information. This register is not rank
specific because multiple devices can be tied to a single signal. If independent status is required, individual GPIO inputs
can be used. The state of the system boot configuration signals BOOT[2:0] are also reflected in mem_ststat.
mem_stndctrl
Offset = 0x1100
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
IE
CS3O CS2O CS1O CS0O
BOOT
Def. 00000000000000000000000000000001
Bits
Name
Description
R/W
Default
31:9
—
Reserved
—
8
IE
NAND-busy interrupt enable.
0
Disable NAND-busy interrupts.
1
Enable NAND-busy interrupts.
W0
7
CS3O
RCS3# override. Setting this bit asserts the chip select.
W
0
6
CS2O
RCS2# override. Setting this bit asserts the chip select.
W
0
5
CS1O
RCS1# override. Setting this bit asserts the chip select.
W
0
4
CS0O
RCS0# override. Setting this bit asserts the chip select.
W
0
3:1
—
Reserved.
—
0
BOOT
NAND-boot mode enable.
0
Disable boot mode
1
Enable boot mode
This bit must be cleared once the bootloader stored in NAND Flash is cop-
ied into cache or external memory.
W1
mem_ststat
Offset = 0x1104
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
PWT EWT
BOOT
BSY
Def. 00000000000000000000000000000000
Bits
Name
Description
R/W
Default
31:6
—
Reserved.
—
5
PWT
PWAIT# status.
0
PWAIT# is not asserted.
1
PWAIT# is asserted.
R0
4
EWT
EWAIT# status.
0
EWAIT# is not asserted.
1
EWAIT# is asserted.
R0
3:1
BOOT[2:0]
System boot configuration state. Reflects the state of the BOOT[2:0] sig-
nals.
RSystem
Dependent
0
BSY
NAND device busy status. The interrupt associated with the RNB signal
(interrupt number 23 on interrupt controller 0) occurs when the NAND
device is ready. The interrupt is enabled by setting mem_stndctrl[IE].
0
RNB is low. NAND device is busy.
1
RNB is high. NAND device is ready.
R0