AMD Alchemy Au1550 Security Network Processor Data Book
113
PCI 2.2 Bus Controller
30283D
4.1.1.3
PCI Back-to-Back Mask, Base0 and Base1, Class Code High, Subsystem ID Registers
Master-initiated fast back-to-back transfers require that the subsequent access is to the same target as the previous
access. The Au1550 processor allows the programmer to set up 2 target back-to-back windows. The Mask Register config-
ures the size of the windows, while the base registers set the base address of each target window. A fast back-to-back
transaction is attempted when:
((physical_addr & b2b_mask == b2b_base0) | (physical_addr & b2b_mask == b2b_base1))
Fast back-to-back is enabled by setting bit 9 of the pci_statcmd register.
pci_b2bmaskcch[CCH] sets the Class Code High field. This field is the upper 16 bits of the Class Code defined by the PCI
2.2 specification. It is combined with the Class Code Low field to form the full 24-bit Class Code. This field can be written
from the processor only and are reflected out to the PCI bus on configuration read cycles to address 0x0008 when the
Au1550 is configured as a satellite.
pci_b2bbase0venid[SVID] sets the Subsystem Vendor ID, and pci_b2bbase1subid[SUBID] is the Subsystem ID. These
fields can be written from the processor only, and allow for identification of different systems which contain an Au1550.
These fields are reflected out to the PCI bus on configuration read cycles to address 0x002C when the Au1550 is config-
ured as a satellite.
pci_b2bmaskcch
Offset = 0x0008
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
B2BMASK
CCH
Def. 00000000000000000000000000000000
Bits
Name
Description
R/W
Default
31:16
B2BMASK
This field is the mask used to qualify fast back to back transfers.
R/W
0
15:0
CCH
Class Code High. These bits are reflected as the upper two bytes of the
class code field in PCI configuration register space pci_classrev[31:16].
R/W
0
pci_b2bbase0venid
Offset = 0x000C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
B2BBASE0
SVID
Def. 00000000000000000000000000000000
Bits
Name
Description
R/W
Default
31:16
B2BBASE0
Specifies a base address for fast back to back transfers.
R/W
0
15:0
SVID
This field is reflected as the subsystem vendor ID in PCI configuration
space.
R/W
0
pci_b2bbase1subid
Offset = 0x0010
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
B2BBASE1
SUBID
Def. 00000000000000000000000000000000
Bits
Name
Description
R/W
Default
31:16
B2BBASE1
Specifies a base address for fast back to back transfers.
R/W
0
15:0
SUBID
This field is reflected as the subsystem ID in PCI configuration space.
R/W
0