176
AMD Alchemy Au1550 Security Network Processor Data Book
Security Engine
30283D
7.3.3.7
Command Queue Status Register
The packet engine internal command queue status register (sec_glbqstat) provides real-time status for the internal com-
mand queue. In general, this register is used for debug purposes, and in the case of packet descriptors being written
directly to the command queue, it can be used to determine when the queue is full.
7.3.3.8
External Ring Status Register
The packet engine external descriptor ring status register (sec_glbextrstat) provides real-time status for the external PDR
(if applicable).
11:0
POLLDIV
Ring Poll Divisor. Sets a binary value that is used to divide-down the main
security engine clock and arrive at the polling frequency. Values of 1 –
4,095 provide valid poll intervals. Clearing POLLDIV disables PDR polling
altogether. (In this case, the Read Descriptor interrupt is the only mecha-
nism for initiating a descriptor poll once an empty descriptor has been
encountered.)
A fixed prescale of 128 is inserted in the main clock prior to the Ring Poll
Divisor.
An example is shown below:
Main security engine clock: 78MHz /128 prescale = 609 kHz
Ring Poll set to 0x0001: Frequency = 609 kHz (1.6 s between polls)
Ring Poll set to 0x0FFF: Frequency = 149 Hz (6.7 ms between polls)
R/W
0
sec_glbqstat
Offset = 0x0058
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
987654321
0
CQA
Def. 0000000000000000000000000000000
1
Bits
Name
Description
R/W
Default
31:1
—
Reserved.
R
0
CQA
Command Queue Available.
0
The command queue is not available.
1
The command queue is available for a descriptor. In target command
mode (sec_glbdmacfg[PE]=0), CQA indicates that the user can
write a new packet descriptor into the command queue.
R1
sec_glbextrstat
Offset = 0x005C
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
INPD
Def. 00000000000000000000000000000000
Bits
Name
Description
R/W
Default
31:26
—
Reserved.
R
0
25:16
INPD
Index of Next Packet Descriptor. These bits indicate the index (0-1023) of
the Next Packet Descriptor to be read by the Packet Engine.
R0
15:0
—
Reserved.
R
0
Bits
Name
Description
R/W
Default