AMD Alchemy Au1550 Security Network Processor Data Book
145
Descriptor-Based DMA (DDMA) Controller
30283D
5.3.2.2
Branch Pointer
This entry in the descriptor contains the upper 4 bits of the starting physical address of the source data used in the compar-
ison. These bits are concatenated with dscr_source0[SPTR] to make the 36-bit physical address. This entry also contains
the pointer to the next descriptor executed when the comparison evaluates true.
15
ARB
0
Low priority pool
1
High priority pool
14:13
DT
Descriptor Type. Selects the descriptor type.
00
Standard descriptor (for source-to-destination transfers)
01
Literal-write descriptor
10
Compare and branch descriptor
11
Reserved
12
SN
Source Non-coherent. Transfers from an internal FIFO on the peripheral bus must be non-coherent.
0
Mark source data as coherent.
1
Mark source data as non-coherent.
11:9
—
Reserved
8
IE
Interrupt Enable.
0
Do not set ddman_irq[IN] upon descriptor completion.
1Set ddman_irq[IN] upon descriptor completion.
7:5
—
Reserved
4
SP
Copy descriptor pointer to status pointer
0
The value written to ddman_statptr is determined by the ST field.
1
Let ddman_statptr = ddman_desptr. The current descriptor status (dscr_stat) is written to
dscr_cmd0 upon descriptor completion.
3
—
Reserved.
2
CV
Clear Valid Bit.
0
Do not clear dscr_cmd0[V] upon descriptor completion.
1Clear dscr_cmd0[V] upon descriptor completion.
1:0
ST
Status Instruction. Determines the information to report when the descriptor completes. The memory con-
tent pointed to by ddman_statptr is changed as follows:
00
No change
01
Write the current descriptor status (dscr_stat).
10
Write the dscr_cmd0 of the current descriptor with the valid bit cleared.
11
Write the remaining byte count.
dscr_branchptr
Offset = 0x04
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9876543210
SUPTR
BPTR
Bits
Name
Description
31:28
SUPTR
Upper Source Pointer. Contains the upper 4 bits of the 36-bit starting physical address of the source data
for the DMA transfer. The upper 4 bits of the 36-bit address must not change during the DMA transfer.
27
—
Reserved.
26:0
BPTR
Branch Pointer. Address bits [31:5] of the next descriptor fetched if the compare evaluates true.
Bits
Name
Description