AMD Alchemy Au1550 Security Network Processor Data Book
121
PCI 2.2 Bus Controller
30283D
4.2.8
Boot from PCI
The Au1550 has the ability to boot from a memory device on PCI. When the BOOT[2:0] signals are 0b100, the Au1550 pro-
cessor fetches the reset vector (0x1FC00000) from PCI memory space. It is required that the boot memory be located at
the Au1550 reset vector physical address. The Au1550 processor may not be the clock source or the PCI reset source sig-
nal (PCI_RSTO# on GPIO[200]) if booting from PCI, since software is required to configure these functions. Also, the inter-
nal arbiter is used when booting from PCI.
4.2.9
PCI Errors
The Au1550 processor error registers (pci_config and pci_erraddr) are intended to be used to supplement the PCI 2.2
Configuration Status bits.
PCI error conditions are reflected in the state of pci_config[ERD, ET, EF, EP, EM, BM]. These bits allow software to deter-
mine if one or more errors occurred and the cause of at least the first error. pci_config[EM] is active only when a second
error of any kind shown occurs—that is, when an error is pending while another error occurs. The EM bit allows software to
know that multiple errors have occurred since the last time the error conditions were cleared. Once errors are cleared, EM
is also cleared so that a subsequent error can be logged as a 'first error'.
Table 4-4 shows the possible error conditions
reflected in pci_config[ERD, ET, EF, EP].
There may be error situations where pci_config and pci_erraddr are not updated when an error occurs. On Au1550 initi-
ated accesses that end in an fatal error, up to two transactions after the error could be discarded because of the asynchro-
nous nature between the PCI bus and the SBUS. However, the address of the transaction to which the fatal error occurred
are captured.
Table 4-4. PCI Error Conditions on pci_config[27:24]
PCI Mode
PCI Error Condition
Bit 27
ERD
Bit 26
ET
Bit 25
EF
Bit 24
EP
Target
Parity Error is detected by the Au1550 processor on a PCI Write
to Au1550 memory (and PCI_PERR# is asserted)
010
1
Master
PCI Master Abort on Configuration Space Read access, due to no
response from target device on PCI_DEVSEL# (no device present
on selected PCI_IDSEL)
101
0
Master
PCI Master Abort on Configuration Space Write access, due to no
response from target device on PCI_DEVSEL# (no device present
on selected PCI_IDSEL)
001
0
Master
PCI Master Abort on any PCI Read Access, due to transaction not
completed in time—address claimed, but PCI_TRDY# or
PCI_STOP# not asserted within the number of clocks pro-
grammed in pci_timeout[TO].
101
0
Master
PCI Master Abort on any PCI Write Access, due to transaction not
completed in time—address claimed, but PCI_TRDY# or
PCI_STOP# not asserted within the number of clocks pro-
grammed in pci_timeout[TO].
001
0
Master
PCI Access retried to the same device signaling RETRY more
than the number of times programmed in pci_timeout[MR].
001
0
Master
PCI Target abort signaled by the addressed Target device
0
1
0
Master
Au1550 processor detects a PCI parity error condition on data
received from a target during a read
100
1
Master
PCI Target signals a PCI parity error condition on PCI_PERR#,
from data received from the Au1550 on a PCI Write Transaction
000
1